1 / 21

Decimal Multiplier on FPGA using Embedded Binary Multipliers

Decimal Multiplier on FPGA using Embedded Binary Multipliers. Authors: H. Neto and M. Vestias Conference: Field Programmable Logic and Applications (FPL), 2008. Presenter: Tareq Hasan Khan ID: 11083577 ECE, U of S Literature review-3 (EE 800). Outline. Motivation

jbulkley
Download Presentation

Decimal Multiplier on FPGA using Embedded Binary Multipliers

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. Decimal Multiplier on FPGA using Embedded Binary Multipliers Authors: H. Neto and M. Vestias Conference: Field Programmable Logic and Applications (FPL), 2008 Presenter: Tareq Hasan Khan ID: 11083577 ECE, U of S Literature review-3 (EE 800)

  2. Outline • Motivation • Proposed Binary-BCD conversion using base-1000 algorithm • BCD multiplier • Results • Conclusion

  3. Motivation • Decimal arithmetic • Human centric application • Precisely present decimal fractions • Software implementations of decimal arithmetic are slower than in hardware • Proposing a BCD multiplier • BCD operands will be converted to Binary • Taking advantage of the efficient embedded binary multipliers (17x17) available in state-of-the-art FPGAs. • A novel method to convert from Binary to BCD is proposed

  4. Outline • Motivation • Proposed Binary-BCD conversion using base-1000 algorithm • BCD multiplier • Results • Conclusion

  5. Binary-BCD conversion using base-1000 algorithm 1. Convert binary number to a number represented in base-1000 2. Convert each base-1000 digit to BCD using the shift and add-3 algorithm

  6. Conversion of Binary number to base-1000

  7. Conversion of Binary number to base-1000…cont.

  8. Binary to base-1000 conversion hardware up to 999x999 b1 b0 b1 c1 c0 d1^ d0^

  9. Binary to base-1000 conversion for higher numbers • The algorithm can be applied iteratively to convert larger binary numbers to base-1000 • Each digit of the result in base-1000, is calculated iteratively according to Horner’s rule

  10. Binary to base-1000 conversion hardware up to 9999 x 9999

  11. Binary to base-1000 conversion hardware up to 99999 x 99999 Multipliers of 17 × 17 size are found on state-of-the-art FPGAs as embedded multipliers. Binary multiplication of 17 × 17 without sign will result 34 bits. Base-1000 digits are converted to BCD by Shift and Add-3 algorithm

  12. Outline • Motivation • Proposed Binary-BCD conversion using base 1000 • BCD multiplier • Results • Conclusion

  13. BCD multiplier • Convert each BCD operands to binary • Multiply the binary numbers • using embedded FPGA binary multiplier • Convert the binary result to BCD • using the proposed binary to BCD through base-1000 algorithm

  14. BCD multiplier…cont

  15. Outline • Motivation • Proposed Binary-BCD conversion using base 1000 • BCD multiplier • Results • Conclusion

  16. Result Implemented on Xilinx Virtex-4 SX35-12 FPGA • Area increases almost linearly with number of BCD digits • Frequency goes from 242 to 222 MHz • Two levels of pipeline

  17. Result…cont • I1 - A binary to base-1000 converter and then a parallel shift and add-3 algorithm for each b-1000 “digit” • I2 - A binary to decimal converter using the parallel shift and add-3 algorithm. • I3 - A binary to decimal converter using the serial shift and add-3 algorithm • I1 (proposed) uses less area (about 60%) than the commonly used I2 • I3 has a very low area occupation, high speed, but higher latency

  18. Result…cont2 • Mult1 - Decimal multiplier with converter I1 (proposed) • Mult2 - Decimal multiplier with converter I2 • Mult3 - Decimal multiplier via carry-save addition • Mult1 (proposed) uses less area (about 65%) than the commonly used Mult2 • Mult1 uses (about 70%) area than Mult3, at the cost of an embedded binary multiplier • All implementation work at frequency near 200MHz

  19. Conclusion • Proposed Binary-BCD conversion algorithm using base-1000 • More area efficient than mostly used shift and add-3 algorithm • BCD multiplier implemented in this work, take advantage of embedded binary multipliers on state-of-the-art FPGAs

  20. Thanks

  21. 24.X + Y hardware block

More Related