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14:332:331 Computer Architecture and Assembly Language Spring 06 Week 2 : ISA, MIPS Assembly

Dive into the world of computer architecture and assembly language with a focus on MIPS instruction set. Explore the fundamentals of MIPS assembly, registers, data paths, and memory addressing. Enhance your knowledge of processor control and execution.

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14:332:331 Computer Architecture and Assembly Language Spring 06 Week 2 : ISA, MIPS Assembly

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  1. 14:332:331Computer Architecture and Assembly LanguageSpring 06Week 2 : ISA, MIPS Assembly [Adapted from Dave Patterson’s UCB CS152 slides and Mary Jane Irwin’s PSU CSE331 slides]

  2. Fetch Exec Decode Review I: Execute Cycle • Q1: How does control know which instruction to fetch? • Q2: who does decode? What happens in decode phase? • Q3: How do control and datapath interact to finish exec phase? • Q4: What does datapath have?

  3. Review II: word length • What does 32-bit architecture mean?

  4. Assembly Language • Language of the machine • More primitive than higher level languages e.g., no sophisticated control flow • Very restrictive e.g., MIPS arithmetic instructions • We’ll be working with the MIPS instruction set architecture • similar to other architectures developed since the 1980's • used by NEC, Nintendo, Silicon Graphics, Sony, … • 32-bit architecture • 32 bit data line and address line • data and addresses are 32-bit

  5. MIPS R3000 Instruction Set Architecture Registers • Instruction Categories • Load/Store • Computational • Jump and Branch • Floating Point • coprocessor • Memory Management • Special R0 - R31 PC HI LO • 3 Instruction Formats: all 32 bits wide OP rs rd sa funct rt OP rs rt immediate OP jump target Q: How many already familiar with MIPS ISA?

  6. MIPS Arithmetic Instruction • MIPS assembly language arithmetic statement add $t0, $s1, $s2 sub $t0, $s1, $s2 • Each arithmetic instruction performs only one operation • Each arithmetic instruction specifies exactly three operands destination  source1 op source2 • Those operands are contained in the datapath’s register file ($t0, $s1,$s2) • Operand order is fixed (destination first)

  7. Compiling More Complex Statements • Assuming variable b is stored in register $s1, c is stored in $s2, d is stored in $s3 and the result is to be left in $s0, and $t0 is a temporary register, what is the assembler equivalent to the C statement h = (b - c) + d

  8. Registers • Registers are • Faster than main memory • Can hold variables so that • code density improves (since registers are named with fewer bits than a memory location) – why is that? • Register addresses are indicated by using $

  9. Register File 5 5 5 32 32 32 src1 addr src1 data src2 addr 32 locations dst addr src2 data write data 32 bits MIPS Register File • Operands of arithmetic instructions must be from a limited number of special locations contained in the datapath’s register file • Holds thirty-two 32-bit registers • With two read ports and • One write port

  10. Naming Conventions for Registers 0 $zero constant 0 1 $at reserved for assembler 2 $v0 expression evaluation & 3 $v1 function results 4 $a0 arguments 5 $a1 6 $a2 7 $a3 8 $t0temporary: caller saves . . . (callee can clobber) 15 $t7 16 $s0 callee saves . . . (caller can clobber) 23 $s7 24 $t8temporary (cont’d) 25 $t9 26 $k0 reserved for OS kernel 27 $k1 28 $gp pointer to global area 29 $sp stack pointer 30 $fp frame pointer 31 $ra return address

  11. Processor Devices Control Input Memory Datapath Output Registers vs. Memory • Arithmetic instructions operands must be registers, — only thirty-two registers provided • What about programs with lots of variables? • Store variables in the memory • Load variables from memory to registers before use; store them back to memory after use.

  12. Accessing Memory • MIPS has two basic data transfer instructions for accessing memory lw $t0, 4($s3) #load word from memory sw $t0, 8($s3) #store word to memory • The data transfer instruction must specify • where in memory to read from (load) or write to (store) – memory address • where in the register file to write to (load) or read from (store) – register destination (source) • The memory address is formed by summing the constant portion of the instruction and the contents of the second register

  13. Processor – Memory Interconnections • Memory is viewed as a large, single-dimension array, with an address • A memory address is an index into the array read addr/ write addr Processor Addressable locations 232 read data Memory write data Q: what should be the smallest addressable unit?

  14. MIPS Data Types Integer: (signed or unsigned) 32 bits Character: 8 bits Floating point numbers: 32 bits Memory addresses (pointers): 32 bits Instructions: 32 bits Bit String: sequence of bits of a particular length 8 bits is a byte 16 bits is a half-word 32 bits (4 bytes) is a word 64 bits is a double-word

  15. Byte Addresses • Since 8-bit bytes are so useful, most architectures address individual bytes in memory memory: 232 bytes = 230 words • Therefore, the memory address of a word must be a multiple of 4 (alignment restriction) 0 1 2 3 Aligned Alignment restriction: requires that objects fall on address that is multiple of their size. Not Aligned

  16. little endian byte 0 3 2 1 0 0 1 2 3 big endian byte 0 Addressing Objects: Endianess and Alignment • Big Endian: leftmost byte is word address IBM 360/370, Motorola 68k, MIPS, Sparc, HP PA • Little Endian: rightmost byte is word address Intel 80x86, DEC Vax, DEC Alpha (Windows NT) msb lsb

  17. . . . 0 1 1 0 24 Memory . . . 0 1 0 1 20 . . . 1 1 0 0 16 . . . 0 0 0 1 12 . . . 0 0 1 0 8 . . . 1 0 0 0 4 . . . 0 1 0 0 0 Data Word Address MIPS Memory Addressing • The memory address is formed by summing the constant portion of the instruction and the contents of the second (base) register lw $t0, 4($s3) #what? is loaded into $t0 sw $t0, 8($s3) #$t0 is stored where? $s3 holds 8

  18. . . . . . . A[3] $s3+12 A[2] $s3+8 A[1] $s3+4 A[0] $s3 Compiling with Loads and Stores • Assuming variable b is stored in $s2 and that the base address of integer array A is in $s3, what is the MIPS assembly code for the C statement A[8] = A[2] - b

  19. Compiling with a Variable Array Index • Assuming A is an integer array whose base is in register $s4, and variables b, c, and i are in $s1, $s2, and $s3, respectively, what is the MIPS assembly code for the C statement c = A[i] - b

  20. MIPS Instructions, so far

  21. 000000 10001 10010 01000 00000 100000 op rs rt rd shamt funct Machine Language - Arithmetic Instruction • Instructions, like registers and words of data, are also 32 bits long • Example: add $t0, $s1, $s2 • registers have numbers $t0=$8, $s1=$17, $s2=$18 • Instruction Format: Can you guess what the field names stand for?

  22. op rs rt rd shamt funct MIPS Instruction Fields • op • rs • rt • rd • shamt • funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits = 32 bits

  23. 35 18 8 24 100011 10010 01000 0000000000011000 op rs rt 16 bit number Machine Language - Load Instruction • Consider the load-word and store-word instructions, • What would the regularity principle have us do? • New principle: Good design demands a compromise • Introduce a new type of instruction format • I-type for data transfer instructions • previous format was R-type for register • Example: lw $t0, 24($s2) Where's the compromise?

  24. Memory Address Location • Example: lw $t0, 24($s2) Memory 0xf f f f f f f f 2410 + $s2 = 0x00000002 0x12004094 $s2 0x0000000c Note that the offset can be positive or negative 0x00000008 0x00000004 0x00000000 data word address (hex)

  25. 43 18 8 24 101011 10010 01000 0000000000011000 op rs rt 16 bit number Machine Language - Store Instruction • Example: sw $t0, 24($s2) • A 16-bit address means access is limited to memory locations within a region of 213 or 8,192 words (215 or 32,768 bytes) of the address in the base register $s2

  26. Assembling Code • Remember the assembler code we compiled for the C statement A[8] = A[2] - b lw $t0, 8($s3) #load A[2] into $t0 sub $t0, $t0, $s2 #subtract b from A[2] sw $t0, 32($s3) #store result in A[8] Assemble the MIPS object code for these three instructions

  27. Review: MIPS Data Types Integer: (signed or unsigned) 32 bits Character: 8 bits Floating point numbers: 32 bits Memory addresses (pointers): 32 bits Instructions: 32 bits Bit String: sequence of bits of a particular length 8 bits is a byte 16 bits is a half-word 32 bits (4 bytes) is a word 64 bits is a double-word

  28. Beyond Numbers • Most computers use 8-bit bytes to represent characters with the American Std Code for Info Interchange (ASCII) • So, we need instructions to move bytes around

  29. op rs rt 16 bit number Loading and Storing Bytes • MIPS provides special instructions to move bytes lb $t0, 1($s3) #load byte from memory sb $t0, 6($s3) #store byte to memory • What 8 bits get loaded and stored? • load byte places the byte from memory in the rightmost 8 bits of the destination register • what happens to the other bits in the register? • store byte takes the byte from the rightmost 8 bits of a register and writes it to a byte in memory

  30. Example of Loading and Storing Bytes • Given following code sequence and memory state (contents are given in hexidecimal), what is the state of the memory after executing the code? add $s3, $zero, $zero lb $t0, 1($s3) sb $t0, 6($s3) Memory 0 0 0 0 0 0 0 0 24 • What value is left in $t0? 0 0 0 0 0 0 0 0 20 0 0 0 0 0 0 0 0 16 1 0 0 0 0 0 1 0 12 • What if the machine was little Endian? 0 1 0 0 0 4 0 2 8 F F F F F F F F 4 0 0 9 0 1 2 A 0 0 Data Word Address (Decimal)

  31. Review: MIPS Instructions, so far

  32. Review: MIPS R3000 ISA • Instruction Categories • Load/Store • Computational • Jump and Branch • Floating Point • coprocessor • Memory Management • Special • 3 Instruction Formats: all 32 bits wide Registers R0 - R31 PC HI LO 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits R format OP rs rd shamt funct rt I format OP rs rt 16 bit number 26 bit jump target OP

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