CS, Tsinghua University

1. Recursively Combine Floorplan and Q-Place in Mixed Mode Placement Based on Circuit‘s Variety of Block Configuration Changqi Yang, Xianlong Hong, Hannah Honghua Yang CS, Tsinghua University Strategic CAD Labs, Intel Corporation EDA Lab., Tsinghua University

2. Content • Motivation • Previous Works • Recursive Design Flow • Algorithms for Each Stage • Experimental Results • Future Work EDA Lab., Tsinghua University

3. Motivation(1) • Integrating more circuit cells into one chip results in MMP(Mixed Mode Placement) problem: • Large scale: vast amount of cells. • Mixed mode: standard cells mixed with blocks to be placed simultaneously. • Floorplan and Placement technology • Floorplan: can obtain overlap-free layout but is the great time-consumer. • Placement: especially Q-Place, can obtain results rapidly, but it is difficult for eliminating overlap between standard cells and blocks. EDA Lab., Tsinghua University

4. Circuits #cells #macro blocks #nets Block area (average) /cell area(average) block2 7094 2 10049 2045 block6 5996 6 10049 872 block8 5662 8 10049 695 block9 5895 9 10049 751 block10 5151 10 10049 676 ibm01 12260 246 14111 57 ibm02 19071 271 19584 157 ibm11 69779 373 81454 166 ibm13 83285 424 99666 162 Motivation(2) • The common solution is the combination of floorplan and Q-Place according to circuit hierarchy. • Another challenge for MMP is the variety of circuit: • The number of blocks varies from 2 to 424 • The size of blocks varies from 57 to 2045 EDA Lab., Tsinghua University

5. Previous Works • HMMP: presented by W.M Wu in ASICON2001 • Generate two-level hierarchy of circuit. • Floorplan on block-level and Q-Place on cell-level. • Fit the block configuration of few but huge blocks. • Fall into the trap of running out of time in floorplan when there are too many blocks in circuit. • MPG-MS presented by J. Cong in ASP-DAC03 • Generate multi-level hierarchy. • Bin-Basedfloorplan is adopted recursively on each level. • Fit the block configuration of numerous blocks • Consume much time because of its Simulated Annealing Process with high time complexity. EDA Lab., Tsinghua University

6. Recursive Design Flow(1) • The presented design flow RMMP completes placement through 3 routines: partition, global placement and detailed placement. • In partition phase, the components and netlist of circuit are analyzed and partitioned recursively to construct a tree of virtual blocks with the root pointing to the whole circuit on the chip. • An operation-selector will travel along through all the nodes of the tree in the order of Deep First Search (DFS). • For the virtual block composed by physical blocks or by child virtual blocks, the selector performs a fixed-outline floorplanner • Otherwise, it performs a Q-Place based placer. EDA Lab., Tsinghua University

7. Partition Floorplan Q-Place Detailed Placement physical block standard cell virtual block Recursive Design Flow(2) EDA Lab., Tsinghua University

8. Algorithms(1) • Partition • Use a bottom up cluster algorithm to create clusters each of which consists of no more than C standard cells: C-control parameter • Use a top down partition algorithm to create partitions • For each of its virtual blocks, involve partition process recursively EDA Lab., Tsinghua University

9. Algorithms(2) • Global Placement • The global placement is the combination of a floorplanner and a Q-Placer which are performed in the charge of an operation selector. • Fixed-Outline Floorplanning • =WL*Len+WR1*Max(ChipX-PX,0)+WR2*Max(ChipY-PY,0), where Len is the total net length, PX and PY are width and height in packing, ChipX and ChipY are width and height of the chip, wL and wR1 as well as wR2 are weighting factors. • CBL – representation of encode for block placement. • the area packed by blocks does not have to be minimized as an objective EDA Lab., Tsinghua University

10. Algorithms(3) • Q-Place • The objective function is the minimization for the total wire length: • The constraints make the cells distribute on the chip evenly • A faster and more stable method FaSa based on Lagrange multipliers to solve the linear constraint quadratic programming problem EDA Lab., Tsinghua University

11. Algorithm(4) • Detailed Placement: After global placement in all virtual blocks, all standard cells and original blocks are placed near their optimum locations. Detailed placement is adopted throughout the whole chip with original blocks aligned to rows previously. • An initial detailed placement is obtained by inheriting cell positions determined by global placement procedure. • Row assignment refining and row evening are interlaced to reduce the wire length in y and x directions respectively, while rows evening and overlap removing are also done within interlaces. • The wire length is reduced further by cell permutation within rows. EDA Lab., Tsinghua University

12. Circuits #cells #macro blocks #nets Block area (average) /cell area(average) block2 7094 2 10049 2045 block6 5996 6 10049 872 block8 5662 8 10049 695 block9 5895 9 10049 751 block10 5151 10 10049 676 ibm01 12260 246 14111 57 ibm02 19071 271 19584 157 ibm11 69779 373 81454 166 ibm13 83285 424 99666 162 Experimental Results(1) EDA Lab., Tsinghua University

13. Circuits HMMP RunTime (s) RMMP RunTime(s) HMMP WireLen (um) RMMP WireLen (um) Impr (wl %) block2 358 320 1.692e6 1.662e6 1.74 block6 382 335 2.029e6 1.556e6 23.30 block8 405 314 2.022e6 1.522e6 24.74 block9 388 295 2.345e6 2.216e6 5.5 block10 388 356 2.131e6 1.376e6 35.4 Experimental Results(2) • RMMP VS HMMP EDA Lab., Tsinghua University

14. Circuits MPG WireLen (um) RMMP WireLen (um) MPG RunTime (min) RMMP RunTime (min) Impr (time %) ibm01 3.01e6 3.16e6 18 11 39 ibm02 7.42e6 6.59e6 32 18 44 ibm11 2.65e7 2.96e7 112 82 27 ibm13 3.77e7 3.94e7 151 105 30 Experimental Results(3) • RMMP VS MPG-MS EDA Lab., Tsinghua University

15. Future Work • Improve algorithms for each stage. • Support polygon in block floorplan • Support placement in rectilinear-region • Optimum timing delay in MMP. EDA Lab., Tsinghua University

16. Thank you EDA Lab., Tsinghua University