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CDF sensors processed on 6” wafers

Die CDF Silizium Sensoren in 6“ Technologie. CDF sensors processed on 6” wafers. DPG Frühjahrstagung Heidelberg, 15. - 19.März 99 Frank Hartmann Institut für Experimentelle Kernphysik. OUTLINE: Material description Masks layout Sensor performances Process related problems Conclusions.

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CDF sensors processed on 6” wafers

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  1. Die CDF Silizium Sensoren in 6“ Technologie CDF sensors processed on 6” wafers • DPG Frühjahrstagung • Heidelberg, 15. - 19.März 99 • Frank Hartmann • Institut für Experimentelle Kernphysik OUTLINE: • Material description • Masks layout • Sensor performances • Process related problems • Conclusions

  2. Sensor Dimensions • Only 1 of these sensor can fit in a 4” wafer. • 6” = cheaper • 6” detectors are even longer than their 4” counterparts • Double sided • AC coupled • PolySi Biased • Single metal • Common P-stops • Thickness 300mu

  3. L4 L2 Masks layout SVXII ISL

  4. Masks layout (details) P-side N-side

  5. Performances • Capacitance • Other parameters:

  6. Coupling capacitor variation across the wafer Problems Uneven metal deposition due to sputtering problems At the edges of the wafer the coupling capacitor falls below specifications

  7. Coupling capacitor breakdown voltage Problems • Creation of pin-holes during operation in test beam • “Weak” coupling capacitor • Different “mix” of wet and dry oxide fixed the problem • Breakdown voltage of ISL sensors is currently under test with respect to bonding force at KA

  8. Leaky strips Problems Isolated strips and regions show high leakage current Leaky strip Good strip Most strips are about 1 nA but a few go as high as mA Log scale

  9. Leaky strips Problems • Breakdown at the Junction edges • Verified with Infrared Camera • Present even on the n-side when defects are present at the p-stops edges • Most likely related to handling and cleaning conditions • Dust • Leaky strips do not affect neighbors • The noise on them follow predictions (proportional to the square root of the current) • Get worse on the p-side if bias is present (MOS effect)

  10. Leaky strips (2) • Dust particles during processing • -> Inaccessible short between implant and p-stop (N-side) • -> fully biased strip • Large effect on p-side strips • Distortion in local field • --> clean room improvements

  11. Problems got fixed Latest deliveries

  12. SVXII and ISL sensors are double side and the bias will be split. PH is a connection of the implant to input of the PA (virtual GND) The PA will then have to deal with a DC coupled strip Current is not driven by the Si but by the bias circuit. Neighbors channels will be noisy. Pin-holes

  13. On the N-side the electric field is weak. The effect is enhanced and up to 5 channels on each side will show higher noise. Pin-holes

  14. Rbias Rint Low interstrip resistance • First appearance at 2nd step of quality control at KA 3MW Leakagecurrent Bias resistor 100nA 10nA Interstrip resistance 200kW 1GW 100kW Solve: add. cleaning (charge up?) Will it remain good after cleaning?

  15. Conclusions • The workable area of a 6” wafer is almost twice the one of a 4” wafer • 6” Silicon performs as well as 4”. • Switching from 4” to 6” can be painful but is surely feasible. • Radiation hardness is the same as 4”. • Availability of material in the market is not an issue.

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