1 / 29

CMOS Circuit Design for Minimum Dynamic Power and Highest Speed

CMOS Circuit Design for Minimum Dynamic Power and Highest Speed. Tezaswi Raja, Dept. of ECE, Rutgers University Vishwani D. Agrawal, Dept. of ECE, Auburn University Michael L. Bushnell, Dept. of ECE, Rutgers University. Research Funded by: A National Science Foundation Grant.

jania
Download Presentation

CMOS Circuit Design for Minimum Dynamic Power and Highest Speed

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. CMOS Circuit Design for Minimum Dynamic Power and Highest Speed Tezaswi Raja, Dept. of ECE, Rutgers University Vishwani D. Agrawal, Dept. of ECE, Auburn University Michael L. Bushnell, Dept. of ECE, Rutgers University Research Funded by: ANational Science Foundation Grant

  2. Talk Outline • Motivation • Objective • Prior Work • New Approach • Results • Conclusion and Future Work Int'l Conf. on VLSI Design, 2004

  3. Motivation • Power consumption due to glitches can exceed 30-40% of total power consumption. • Existing linear programming techniques eliminate glitches, but may insert delay buffers when overall circuit delay is constrained. • Delay buffers consume power themselves and thus reduce power saving – also chip area increases. • Example: c1355, a 619-gate circuit needed 224 buffers -- 36 % increase in gates– for 42% power saving and no IO delay increase. Int'l Conf. on VLSI Design, 2004

  4. Problem Statement • Find a linear program (LP) to determine gate delays in a CMOS circuit such that: • All glitches are eliminated • No delay buffers are inserted in the circuit • Circuit operates at the highest possible speed permitted by the device technology. Note: The objective is to minimize switching power. Hence, no attempt is made to reduce short-circuit and leakage power, which is an order of magnitude lower for present CMOS technologies; those components of power may be addressed in the future research. Int'l Conf. on VLSI Design, 2004

  5. CMOS Power Dissipation V • Short circuit power • Leakage power (IDDQ) • Dynamic power • Essential transitions • Glitches • Each transition dissipates CV2/2 • Short circuit and leakage power components are at least an order of magnitude lower than the dynamic power in present day technologies. C Int'l Conf. on VLSI Design, 2004

  6. What Are Glitches? Delay =1 • Glitches occur due to differential (unbalanced) path delays. • Glitches are transients that are unnecessary for the correct functioning of the circuit. • Glitches waste power in CMOS circuits. 2 2 Int'l Conf. on VLSI Design, 2004

  7. Glitch Suppression Path P1 • Differential Path Delay Path P2 • Differential Delay = |delay (P1) – delay (P2)|; it is the width of the maximum potential glitch at the gate output. • For complete glitch suppression: for each gate, inertial delay > differential delay • To satisfy this condition, previous low-power design methods insert delay buffers in the circuit. • Power will be further reduced if glitch suppression could be achieved without buffers. Int'l Conf. on VLSI Design, 2004

  8. Example: Why Use Buffers? 1 Critical path delay = 3 • Delay unit is the smallest delay possible for a gate in a given technology. • Critical Path is the longest delay path in the circuit and determines the speed of the circuit. 1 1 Int'l Conf. on VLSI Design, 2004

  9. Example (cont.) 0 1 • For glitch free operation of first gate: • Differential delay at inputs  inertial delay • OK 0 1 time 1 Int'l Conf. on VLSI Design, 2004

  10. Example (cont.) 1 1 1 0 1 • For glitch free operation of second gate: • Differential delay at inputs  inertial delay • OK Int'l Conf. on VLSI Design, 2004

  11. Example (cont.) 1 1 2 1 0 • For glitch free operation of third gate: • Differential delay at inputs  inertial delay • Not true for gate 3 Int'l Conf. on VLSI Design, 2004

  12. Example (cont.) 1 1 2 1 1 1 • For glitch free operation with no IO delay increase:Must add a delay buffer. • Buffer is necessary for conventional gate design – only gate output delay is controllable. Int'l Conf. on VLSI Design, 2004

  13. Controllable Input Delay Gates 1 1 2 1 2 0 • Assume gate input delays to be controllable • Glitches can be suppressed without buffers Int'l Conf. on VLSI Design, 2004

  14. Delay Model for a New Gate d3,1 + d3 1 3 • Separate the output (inertial) and input delay components. • d3 - output delay of the gate. • d3,1- input delay of the gate along path from 1 to 3. • Gate design is feasible and is under development... • Technology constraint: input delay difference has an upper bound, which we define as Gate Input Differential Delay Upper Bound ( ub ). d3,2 + d3 2 Int'l Conf. on VLSI Design, 2004

  15. Gate Input Differential Delay Upper Bound (ub) • It is a measure of the maximum difference in delay of any two IO paths through the gate, that can be designed in a given CMOS technology. • Arbitrary input delays cannot be realized in practice due to the technology limitation at the transistor and layout levels. • The bound ub is the limit of flexibility allowed by the technology to the designer at the transistor and layout levels. • The following feasibility condition must be imposed while determining delays for glitch suppression: 0  di, j  ub Int'l Conf. on VLSI Design, 2004

  16. A New Linear Program • Contains following components • Variables • Gate inertial delay variables (di) • Input delay variables (di,j) • Timing window variables • Constraints • Gate delay constraints • Gate input delay upper bound constraints • Differential delay constraints • Maximum delay constraints • Objective function • Let us consider a simple example combinational circuit. Int'l Conf. on VLSI Design, 2004

  17. New LP Example d5,1 + d5 5 1 d7,5 + d7 7 d5,2 + d5 2 d7,6 + d7 d6,2 + d6 d7,4 + d7 3 6 d6,3 + d6 4 • Gate inertial delay variables d5 ..d7 • Gate input delay variables di, j for every path through gate i from input j • Corresponding window variables t5 ..t7 and T5 ..T7. Int'l Conf. on VLSI Design, 2004

  18. New LP Example (cont.) d5,1 + d5 5 1 d7,5 + d7 7 d5,2 + d5 2 d7,6 + d7 d6,2 + d6 d7,4 + d7 6 3 d6,3 + d6 4 • Inertial delay constraint for gate 5: d5 1 • Input delay constraints for gate 5: • 0  d5,1  ub • 0  d5,2  ub Int'l Conf. on VLSI Design, 2004

  19. New LP Example (cont.) d5,1 + d5 5 1 d7,5 + d7 d5,2 + d5 7 2 d7,6 + d7 d6,2 + d6 d7,4 + d7 6 3 d6,3 + d6 4 • Differential delay constraints for gate 5: T5> T5,1 + d5; t5 < t5,1 + d5; d5> T5 – t5; T5> T5,2 + d5; t5 < t5,2 + d5; Int'l Conf. on VLSI Design, 2004

  20. New LP Example (cont.) d5,1 + d5 5 1 d7,5 + d7 d5,2 + d5 7 2 d7,6 + d7 d6,2 + d6 d7,4 + d7 6 3 d6,3 + d6 4 • Differential delay constraints for gate 5: T5,1> T5 + d5,1; T5,2> T5 + d5,2; t5,1 < t5 + d5,1; t5,2 < t5 + d5,2; Int'l Conf. on VLSI Design, 2004

  21. New LP Example (cont.) d5,1 + d5 1 5 d7,5 + d7 d5,2 + d5 7 2 d7,6 + d7 d6,2 + d6 d7,4 + d7 6 3 d6,3 + d6 4 • IO delay constraint for each PO in the circuit: T7maxdelay; maxdelay is the parameter which gives the delay of the critical path. This determines the speed of operation of the circuit. Int'l Conf. on VLSI Design, 2004

  22. New LP Example (cont.) 5 d5,1 + d5 1 d7,5 + d7 7 d5,2 + d5 2 d7,6 + d7 d6,2 + d6 d7,4 + d7 6 3 d6,3 + d6 4 • Objective Function: minimizemaxdelay; • This gives the fastest and lowest dynamic power consuming circuit, given the feasibility condition for the technology. Int'l Conf. on VLSI Design, 2004

  23. Solution Curves Power Previous solutions with buffers Power consumed by buffers New solutions ub= ∞ ub=5 ub=0 Minimum Dynamic power ub=10 ub=15 Fastest Possible Design Maxdelay Int'l Conf. on VLSI Design, 2004

  24. Results: Procedure Outline Combinational circuit netlist C++ Program Constraint-set AMPL Optimized delays Power Estimator Results Int'l Conf. on VLSI Design, 2004

  25. Results on Feasibility Upper Bound (ub) • Maxdelay is normalized to the fastest possible circuit design. • Each curve is a different benchmark circuit. • As we increase ub, the circuit becomes faster. • Flexibility required for fastest operation of circuit is proportional to the size of the circuit. Int'l Conf. on VLSI Design, 2004

  26. Results: Low-Power Design Int'l Conf. on VLSI Design, 2004

  27. Comparison with Conventional Gate Design (ub=0) (Raja et al., VLSI Des. `03) Int'l Conf. on VLSI Design, 2004

  28. Conclusion • Main idea: Minimum dynamic power circuits can be designed if gates with variable input delays are used. • The new design suppresses all glitches without any delay buffers. • Speed of the new design depends on the gate input delay variability allowed by the technology. • A linear program solution demonstrates the idea. • Results show average power savings up to 52%. • Future work: Variable input delay gate design. Int'l Conf. on VLSI Design, 2004

  29. Thank you Int'l Conf. on VLSI Design, 2004

More Related