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Introduction to vhdl a basic introduction

Introduction to VHDL(A Basic Introduction)

Mr. Scott, have you always multiplied your repair estimates by a factor of four?

Use and distribution notice
Use and Distribution Notice

  • Possession of any of these files implies understanding and agreement to this policy.

  • The slides are provided for the use of students enrolled in Jeff Six's Computer Architecture class (CMSC 411) at the University of Maryland Baltimore County. They are the creation of Mr. Six and he reserves all rights as to the slides. These slides are not to be modified or redistributed in any way. All of these slides may only be used by students for the purpose of reviewing the material covered in lecture. Any other use, including but not limited to, the modification of any slides or the sale of any slides or material, in whole or in part, is expressly prohibited.

  • Some of the material in these slides, including the examples, is derived from VHDL for Programmable Logic and The Designer’s Guide to VHDL. Credit is hereby given to the authors of these textbooks for much of the content. This content is used here for the purpose of presenting this material in CMSC 411, which uses this textbook.

Modeling a hardware system
Modeling a Hardware System

  • A hardware system can be described using a model, consisting of an entity declaration and architecture bodies.



Architecture Bodies

Entity declarations and architecture bodies
Entity Declarations and Architecture Bodies



  • The entity declaration specifies what the system being modeled looks like from the outside (black box view).

  • An architecture body is one possible implementation of that entity.

Architecture Bodies

Example an 8 bit equality comparator
Example: An 8-bit Equality Comparator

  • Here is a schematic symbol for such a comparator (let’s call it eqcomp8).




Example the entity declaration
Example:The Entity Declaration

  • The entity declaration for this model is quite simple. In VHDL,

entity eqcomp8 is

port ( a: in bit_vector (7 downto 0)

b: in bit_vector (7 downto 0)

equals: out bit );

-- equals is active high

end eqcomp8;

The entity declaration
The Entity Declaration

  • A couple observations concerning the entity declaration…

    • entity, port, is – these are keywords/reserved words in VHDL

    • -- (2 hyphens) is the comment syntax – everything past the -- to the end of the line is a comment (like // in the C++ language)

    • a, b are input 8-bit bit vectors

    • equals is an output bit

  • The entity declaration describes the entity being modeled – it’s a black box view.

Example the architecture body
Example:The Architecture Body

  • The architecture body for this model is also quite simple. In VHDL,

architecture dataflow of eqcomp8 is


equals <= ‘1’ when (a = b) else ‘0’;

end dataflow;

The architecture body
The Architecture Body

  • Observations about the architecture body…

    • The is the architecture known as “dataflow” of the entity known as “eqcomp8”.

    • The one line in the body can be interpreted as “if the value of bus A equals the value of bus B then equals is assigned the value of ‘1’, otherwise ‘0’.

    • In VHDL, the high subscript line on a bus is the most significant (i.e. A(7) is the most significant bit of the value carried on the bus known as A).

Entity declarations revisited
Entity Declarations Revisited

  • The entity declaration specifies the interfaces of the design (the input and output).

  • As another example, the entity declaration of a 4-bit adder could be written as…

entity add4 is port(

a, b: in std_logic_vector(3 downto 0);

cin: in std_logic;

sum: out std_logic_vector(3 downto 0);

cout: out std_logic);

end add4;

Port maps and modes
Port Maps and Modes

  • These port declarations describe the signals coming in and out of the entity.

  • The mode describes the direction in which data is transferred through a port…

    • in – data flows into the entity

    • out – data flows out of the entity

    • buffer – data flows out but is also available for internal feedback (can act as a driver within the architecture body)

      • data only flows out – cannot drive this signal externally

      • may not have multiple drivers

    • in/out – can do all of the above (really do not want to do this unless you need to)

Architecture bodies
Architecture Bodies

  • An architecture body can be written in one of three different forms/models…

    • behavioral – written as a set of sequential assignment statements and is used to model the behavior of the system

    • dataflow – written as a set of concurrent assignment statements and is used to model the paths by which data flows in the system

    • structural – written as a set of interconnected components and is used to model the internal structure of the system

Behavioral modeling
Behavioral Modeling

  • The behavioral model is written as a set of sequential assignment statements.

  • This is known as a high-level description of the system being modeled and is very similar to a sequential algorithm programmed in a C-like language.

  • A behavioral description has one or more process statements (procedures), each with a sensitivity list.

    • When any of the input signals specified in the sensitivity list changes, the process statement will run and (possibly) change the output signals.

Behavioral modeling example
Behavioral Modeling Example

library ieee;

use ieee.std_logic_1164.all;

entity eqcomp8 is port (

a,b: in std_logic_vector(7 downto 0);

equals: out std_logic);

end eqcomp8;

architecture behavioral of eqcomp8 is (


comp: process (a,b)


if a = b then equals <= ‘1’;

else equals <= ‘0’;

end if;

end process comp;

end behavioral;

Another behavioral modeling example
Another Behavioral Modeling Example

architecture behavioral of register2 isbegin

storage : process isvariable internal_data0, internal_data1 : bit;beginif en = '1' and clk = '1' then internal_data0 := data0; internal_data1 := data1;end if; q0 <= internal_d0 after 5 ns; q1 <= internal_d1 after 5 ns;

wait on data0, data1, en, clk;end process storage;

end architecture behavioral;

More on behavioral models
More on Behavioral Models

  • This is a behavioral model of a 2 bit register.

  • We do a couple new things here…

    • The process has two internal variables (they will end up as flip/flops in hardware).

    • Some of the assignment statements are in a conditional statement – they only have an effect if the conditional is true when the process runs.

    • We added a wait keyword in our output assignments – this models the propagation delay inherit in that datapath.

    • The sensitivity list is implemented as a wait on statement at the end of the process (but it works the same way as putting these signals in parens at the beginning of the process statement).

Behavioral descriptions
Behavioral Descriptions

  • Is there any difference between these two behavioral descriptions?

architecture behavioral of eqcomp8 is


comp: process (a,b)


equals <= ‘0’;

if a = b then

equals <= ‘1’;

end if;

end process comp;

end behavioral;

architecture behavioral of eqcomp8 is


comp: process (a,b)


if a = b then

equals <= ‘1’;

end if;

equals <= ‘0’;

end process comp;

end behavioral;


A process statement is sequential!

Dataflow modeling
Dataflow Modeling

  • The dataflow model is written as a set of concurrent assignment statements.

  • It specifies how data is transferred through the system.

  • There are no process statements. Rather dataflow modeling using simple equations, when-else, with-select-when, and some other forms.

  • These statements are evaluated concurrently, not sequentially!

Dataflow modeling example
Dataflow Modeling Example

library ieee;

use ieee.std_logic_1164.all;

entity eqcomp8 is port (

a,b: in std_logic_vector(7 downto 0);

equals: out std_logic);

end eqcomp8;

architecture dataflow of eqcomp8 is (


equals <= ‘1’ when (a = b) else ‘0’;

-- equals is active high

end dataflow;

Another dataflow modeling example
Another Dataflow Modeling Example

  • As another example, a dataflow model of a full adder could be written.

  • Here we add the after keyword which models propagation delay for that datapath.

  • Note that we do not use “dataflow” as the name of our architectural body – it’s just a name.

architecture my_full_adder of full_adder is (


sum <= a xor b xor cin after 15ns;

cout <= (a and b) or (b and cin) or (a and cin) after 10ns;

end my_full_adder;

Structural modeling
Structural Modeling

  • The structural model is a VHDL netlist (this is like a schematic netlist).

  • Individual components are instantiated.

  • This is a hierarchical type design…

    • Each component present in the structural model can be individually design and simulated – the model then tied them all together using a netlist (which port connects to which port).

    • The structure of the logic is completely specified.

Structural modeling example
Structural Modeling Example

  • Here is an example of a structural model…

Port maps
Port Maps

  • In a structural model, the port map statement connects signals to input and output ports on components.

  • In the example, the first 2 input XOR gate (xor2) has its two inputs connected to a(0) and b(0) and its output connected to c(0). Similar connections exits for the other bits in the a, b, and c signals.

  • The c signals are then connected to the 4 input NOR (nor4) inputs and the output of that gate is connected to the aeqb signal.

  • All the port map statements do is connect ports and wires, defining the entity’s structure.

Back to the basics
Back to the Basics

  • Now that we dove in and looked at the three ways of constructing models in VHDL and some simple examples, let’s take a step back and look at some basics of the VHDL language.

  • VHDL = Very High Speed Integrated Circuit Hardware Description Language.

    • Started life in the 1970s as part of the DoD’s VHSIC program

    • Now an IEEE standard (set of standards, actually)


  • Identifiers (names of things) in VHDL must follow certain rules…

    • The first character must be a letter.

    • The last character cannot be an underscore.

    • Two underscores in succession are not allowed.

    • Reserved words/keywords cannot be used as identifiers.

Signals and variables
Signals and Variables

  • A signal is a wire.

    • A signal is not updated until the end. Although a sequential signal assignment causes a transaction to be scheduled, it is only the last transaction on that signal that has any effect.

  • A variable is not a wire.

    • A variable is used only in processes/subprograms. It does not represent a wire and is typically used for high-level modeling. It stores values.

    • A variable assignment happens immediately.

  • Declaring them is almost the same…

signal count : bit_vector(3 downto 0)

variable count : bit_vector(3 downto 0)

Enumeration types
Enumeration Types

  • Enumeration types can be created in VHDL…

    • Some simple examples…

      • type color is (red, black, blue);

      • type suite is (hearts, spades, clubs, diamonds);

    • IEEE 1076 introduces a few…

      • type boolean is (false, true);

      • type bit is (‘0’, ‘1’);

Record types
Record Types

  • A record type can be created…

type io_bundle is record

data: bit_vector (7 downto 0);

enable: bit;

control: bit_vector (3 downto 0);

end record;

signal bus_a: io_bundle;

signal bus_b: io_bundle;

Logic types
Logic Types

  • The standard bit and bit_vector represent 0 or 1 (or a vector of 0/1).

  • The IEEE 1164 standard describes std_logic, which represents a physical wire/signal…

type std_logic is ( ‘U’ -- undefined

‘X’ -- forcing unknown

‘0’ -- forcing 0

‘1’ -- forcing 1

‘Z’ -- high impedance

‘W’ -- weak unknown

‘L’ -- weak 0

‘H’ -- weak 1

‘-’ -- don’t care );

Notice that

std_logic is an


type, itself. It

is used to represent

physical wire states.


  • VHDL supports attributes which allow the direct access to parts of a signal or data type…

type count is integer range 0 to 127;

type states is (idle, decision, read, write);

type word is array (15 downto 0) of std_logic;

Attributes and their return values

A more complex example
A More Complex Example

  • Let’s look at a 4-input multiplexer.

  • Here, we use concurrent assignment statements.

  • What style model is this?

The with select when statement
The with-select-when Statement

  • Let’s introduce a selective signal assignment statement. This is used as a concurrent statement in VHDL (not in a sequential process).

  • Some rules must be followed…

    • The statement is a with-select-when.

    • All selection signals must be listed.

    • All selection signal values must be mutually exclusive.

    • Changes in any signal will cause the evaluation.

Rewriting the multiplexer
Rewriting the Multiplexer

  • We can rewrite our 4-bit multiplexer using the with-select-when statement to make it much simpler.

A little more robustness
A Little More Robustness

  • We can make our design a little more robust by introducing an undefined output with an invalid input…

  • The ‘-’ value is defined in std_logic as “undefined”. So, if an invalid input is detected, the output will be undefined.

  • Note that here an invalid input is impossible, but this is still a good practice.

The when else statement
The when-else Statement

  • Let’s introduce a conditional signal assignment statement. This is used as a concurrent statement in VHDL (not in a sequential process).

  • Some rules must be followed…

    • The statement is a when-else.

    • The signal is assigned the first value when the condition is true.

    • The conditions do not have to be mutually exclusive.

Rewriting the multiplexer1
Rewriting the Multiplexer

  • We can rewrite the multiplexer using when-else statements…

A simple hardware system
A Simple Hardware System?

  • Remember that when-else statements do not need to be mutually exclusive.

  • Let’s look at a simple statement and the (quite complex) synthesis result…

What happened
What Happened?

  • Since the conditions are not mutually exclusive, complex hardware is created to deal with priority (the first condition in the when-else takes precedence over the second, etc…).

  • If we use a mutually exclusive form, the design can become a lot simpler…

Sequential statements
Sequential Statements

  • We have seen some concurrent statements, now let’s look at sequential statements using in a process.

  • The if statement is used here…

If statement example
If Statement Example

  • Are these two process statements the same?


Sequential execution of

these two processes

yields the same value

being assigned to the

step output.

Lack of a default value
Lack of a Default Value

  • Here is a different type of example…what will the hardware for this process statement yield? Why is this hardware synthesized?

Since there is no value assigned if addr

is <= “0F,” step will retain its value.

The else if statement
The else-if Statement

  • This is why the elsif part of the if statement is present in VHDL…

Rewriting the multiplexer again
Rewriting the Multiplexer(again)

  • Rewriting the multiplexer using the if/elsif/else statement…

Another if elsif else example
Another if/elsif/else Example

  • Let’s implement an address decoder that takes an address as input and then specifies which device controls the range of memory that address falls in.

The case when statement
The case-when Statement

  • For cases where there are multiple input combinations and the outputs should behave differently based on those input combinations, the case-when statement can be used.

Modeling sequential logic
Modeling Sequential Logic

  • Let’s build a D flip/flop.

  • Note that this is an edge-triggered flip/flop. We are using the event attribute on the clk signal – this is true is the clk signal is the signal that changed and caused the process to run.

Modeling a register
Modeling a Register

  • Note that it is trivial to model an 8-bit register in place of the flip/flop…

Modeling a t flip flop
Modeling a T Flip/Flop

  • We can model a T flip/flop easily as well…

The rising edge function
The rising_edge Function

  • Realizing that the combination of the event attribute and a signal level comparison are a popular combination, VHDL has the rising_edge (and falling_edge) function…

Asynchronous logic in a process statement
Asynchronous Logic in a Process Statement

  • We can introduce asynchronous logic to our flip/flop – let’s add an async reset…

A synchronous reset
A Synchronous Reset

  • We could add a synchronous reset instead…

Combining the resets
Combining the Resets

  • We could do both (async for 0 and sync for 1) – and let’s do it with our 8-bit register…

Modeling an 8 bit counter
Modeling an 8-bit Counter

  • We can model an 8-bit counter with…

    • Asynchronous set to “0011010”

    • Synchronous load and enable inputs

    • Sensitive to grst and txclk signals

The 8 bit counter
The 8-bit Counter

  • This simple model synthesizes to…

Extending the counter
Extending the Counter

  • We can add a preset capability…

The aggregate statement
The Aggregate Statement

  • Notice that we use the statement

    cnt <= (others => ‘0’);

  • The (others => ‘0’) is known as an aggregate – a list of elements in parens, separated by commas, in which all elements of the vector are defined as ‘0’. For instance, in this VHDL code,

    signal a: std_logic_vector(7 downto 0);

    a <= (‘1’, ‘0’, others <= ‘1’);

    the signal a gets assigned the value “10111111”.

Three state output

When output is enabled, we get

output. Otherwise, high impedance.

Three-State Output

  • We can add an output enable to our counter…

Oes: process (oe, cnt)


if oe = ‘0’ then

cnt_out <= (others => ‘Z’);


cnt_out <= cnt;

end if;

end process oes;

end archcnt8;

The inout signal mode
The InOut Signal Mode

  • We can use the same connections for count and data (output and load input)…

Testbench development
Testbench Development

entity test_bench isend entity test_bench;

architecture test_register2 of test_bench is

signal d0, d1, en, clk, q0, q1, : bit;


dut : entity register2(behavioral)port map ( d0, d1, en, clk, q0, q1 );

stimulus : process isbegin d0 <= ’1’; d1 <= ’1’; wait for 20 ns; en <= ’0’; clk <= ’0’; wait for 20 ns; en <= ’1’; wait for 20 ns; clk <= ’1’; wait for 20 ns; d0 <= ’0’; d1 <= ’0’; wait for 20 ns; en <= ’0’; wait for 20 ns; …wait;end process stimulus;

end architecture test_register2;

  • To test our VHDL components, a testbench can be used.

  • This is a set of tests that exercises the components to verify that they work correctly.

The testbench entity and architecture
The Testbench Entityand Architecture

entity test_bench isend entity test_bench;

architecture test_register2 of test_bench is

signal d0, d1, en, clk, q0, q1, : bit;


dut : entity register2(behavioral)port map ( d0, d1, en, clk, q0, q1 );

stimulus : process isbegin

  • Our entity declaration shows no inputs and no outputs for our testbench.

  • The entity and port map statements creates an instance of the register2 entity with the behavioral model and connects the specified signals to the corresponding ports on the entity.

Design verification
Design Verification

  • Once the entities we want to test have been instantiated, the process statement is a set of sequential statements to fully exercise the component.

  • A series of test values can be applied to the inputs of the entities under test and the results examined…

    • using a simulator to observe the outputs and intermediate signals

    • by designing a process that itself verifies the correct operation of the entities

Regression testing
Regression Testing

  • Regression testing is the process of verifying that a new refinement of a design functions the same as the model it is replacing.

    • Two different architectures of the same entity can be tested to make sure they function the same.

  • A testbench for this type of testing normally instantiates two versions on an entity, provides the same inputs and compares the outputs.

  • If the timing characteristics of the two models are not identical, this must be taken into consideration.

Regression test example
Regression Test Example

architecture regression_test of test_bench is

signal data0, data1, en, clk : bit;signal q0a, q1a, q0b, q1b : bit;


arch_a : entity register2(structural)port map ( d0, d1, en, clk, q0a, q1a );

arch_b : entity register2(behavioral)port map ( d0, d1, en, clk, q0b, q1b );

test_all_cases : process isbegin d0 <= ’1’; d1 <= ’1’; wait for 20 ns; en <= ’0’; clk <= ’0’; wait for 20 ns; en <= ’1’; wait for 20 ns; clk <= ’1’; wait for 20 ns; … -- and so on; simulate all possible inputswait;end process test_all_cases;

Regression test example continued
Regression Test Example(continued)

verify_results : process isbeginwait for 10 ns;assert q0a = q0b and q1a = q1b report ”tested implementations produced different results”severity error;wait on d0, d1, en, clk;end process verify_results;

end architecture regression_test;

  • Here, the process test_all_cases iterates through all possible d0 and d1 values (which are fed into both architectures of the register).

  • The verify_results process tests to make sure the outputs are all the same.


  • VHDL benefits…

    • It is powerful and flexible.

    • It is portable and standardized.

    • It reduces time-to-market and drastically reduces the likelihood of fabrication of flawed hardware (due to simulation).

  • VHDL concerns and issues…

    • Less control of gate-level implementation.

    • Synthesis may produce inefficient hardware.

    • Quality of synthesis and simulation depends on the tools that are being used.