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048866: Packet Switch Architectures

048866: Packet Switch Architectures. Maximal Matchings. Dr. Isaac Keslassy Electrical Engineering, Technion isaac@ee.technion.ac.il http://comnet.technion.ac.il/~isaac/. Achieving 100% throughput. Switch model Uniform traffic Technique: Uniform schedule (easy)

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048866: Packet Switch Architectures

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  1. 048866: Packet Switch Architectures Maximal Matchings Dr. Isaac Keslassy Electrical Engineering, Technion isaac@ee.technion.ac.il http://comnet.technion.ac.il/~isaac/

  2. Achieving 100% throughput • Switch model • Uniform traffic • Technique: Uniform schedule (easy) • Non-uniform traffic, but known traffic matrix • Technique: Non-uniform schedule (Birkhoff-von Neumann) • Unknown traffic matrix • Technique: Lyapunov functions (MWM) • Faster scheduling algorithms • Technique: Speedup (maximal matchings) • Technique: Memory and randomization (Tassiulas) • Technique: Twist architecture (buffered crossbar) • Accelerate scheduling algorithm • Technique: Pipelining • Technique: Envelopes • Technique: Slicing • No scheduling algorithm • Technique: Load-balanced router 048866 – Packet Switch Architectures

  3. Complexity of Maximum Matchings • Maximum Size Matchings: • Typical complexity O(N2.5) • Maximum Weight Matchings: • Typical complexity O(N3) • In general: • Hard to implement in hardware • Slooooow. • Can we find a faster algorithm? A. Schrijver, “A Course in Combinatorial Optimization” 048866 – Packet Switch Architectures

  4. Maximal Matching • A maximal matching is a matching in which each edge is added one at a time, and is not later removed from the matching. • i.e. no augmenting paths allowed (they remove edges added earlier) • Consequence: no input and output are left unnecessarily idle. 048866 – Packet Switch Architectures

  5. Example of Maximal Matching A 1 A 1 A 1 2 B 2 B 2 B 3 C 3 C 3 C 4 D 4 4 D D 5 E 5 5 E E 6 F 6 6 F F Maximal Size Matching Maximum Size Matching 048866 – Packet Switch Architectures

  6. Properties of Maximal Matchings • In general, maximal matching is much simpler to implement, and has a much faster running time. • A maximal size matching is at least half the size of a maximum size matching. (Why?) • We’ll study the following algorithms: • Greedy LQF • WFA • PIM • iSLIP 048866 – Packet Switch Architectures

  7. Greedy LQF • Greedy LQF (Greedy Longest Queue First) is defined as follows: • Pick the VOQ with the most number of packets (if there are ties, pick at random among the VOQs that are tied). Say it is VOQ(i1,j1). • Then, among all free VOQs, pick again the VOQ with the most number of packets (say VOQ(i2,j2), with i2≠ i1, j2≠ j1). • Continue likewise until the algorithm converges. • Greedy LQF is also called iLQF (iterative LQF) and Greedy Maximal Weight Matching. 048866 – Packet Switch Architectures

  8. Properties of Greedy LQF • The algorithm converges in at most N iterations. (Why?) • Greedy LQF results in a maximal size matching. (Why?) • Greedy LQF produces a matching that has at least half the size and half the weight of a maximum weight matching. (Why?) 048866 – Packet Switch Architectures

  9. WFA (Wave Front Arbiter)[Tamir and Chi, 1993] Requests Match 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 048866 – Packet Switch Architectures

  10. Wave Front Arbiter Requests Match 048866 – Packet Switch Architectures

  11. Wave Front ArbiterImplementation 2,4 3,4 1,4 4,4 4,3 4,2 1,1 1,2 1,3 2,1 2,3 3,1 3,2 3,3 4,1 2,2 Simple combinational logic blocks 048866 – Packet Switch Architectures

  12. Wave Front ArbiterWrapped WFA (WWFA) N steps instead of 2N-1 Match Requests 048866 – Packet Switch Architectures

  13. Wavefront ArbitersProperties • Feed-forward (i.e. non-iterative) design lends itself to pipelining. • Always finds maximal match. • Usually requires mechanism to prevent Q11 from getting preferential service. • In principle, can be distributed over multiple chips. 048866 – Packet Switch Architectures

  14. Parallel Iterative Matching[Anderson et al., 1993] Iteration: 1 1 1 1 2 2 2 2 #1 1 1 3 3 3 3 2 2 4 4 4 4 f2: Grant f3: Accept/Match 3 3 1 1 1 1 1 1 4 4 2 2 2 2 2 2 #2 3 3 3 3 3 3 4 4 4 4 4 4 uar selection uar selection f1: Requests 048866 – Packet Switch Architectures

  15. PIM Properties • Guaranteed to find a maximal match in at most N iterations. (Why?) • In each phase, each input and output arbiter can make decisions independently. • In general, will converge to a maximal match in < N iterations. • How many iterations should we run? 048866 – Packet Switch Architectures

  16. Parallel Iterative MatchingConvergence Time Number of iterations to converge: Anderson et al., “High-Speed Switch Scheduling for Local Area Networks,” 1993. 048866 – Packet Switch Architectures

  17. Parallel Iterative Matching 048866 – Packet Switch Architectures

  18. Parallel Iterative Matching PIM with a single iteration 048866 – Packet Switch Architectures

  19. Parallel Iterative Matching PIM with 4 iterations 048866 – Packet Switch Architectures

  20. iSLIP[McKeown et al., 1993] 1 4 2 1 1 1 1 3 2 2 2 2 #1 1 1 3 3 3 3 2 2 4 4 4 4 F2: Grant F3: Accept/Match 3 3 1 1 1 1 1 1 4 4 2 2 2 2 2 2 #2 3 3 3 3 3 3 4 4 4 4 4 4 F1: Requests 048866 – Packet Switch Architectures

  21. iSLIP Operation • Grant phase: Each output selects the requesting input at the pointer, or the next input in round-robin order. It only updates its pointer if the grant is accepted. • Accept phase: Each input selects the granting output at the pointer, or the next output in round-robin order. • Consequence: Under high load, grant pointers tend to move to unique values. 048866 – Packet Switch Architectures

  22. iSLIPProperties • Random under low load • TDM under high load • Lowest priority to MRU (most recently used) • 1 iteration: fair to outputs • Converges in at most N iterations. (On average, simulations suggest < log2N) • Implementation: N priority encoders • 100% throughput for uniform i.i.d. traffic. • But…some pathological patterns can lead to low throughput. 048866 – Packet Switch Architectures

  23. iSLIP 048866 – Packet Switch Architectures

  24. iSLIP 048866 – Packet Switch Architectures

  25. iSLIPImplementation Programmable Priority Encoder 1 State 1 log2N Decision N Grant Accept 2 2 N Grant Accept log2N N N Grant Accept log2N N 048866 – Packet Switch Architectures

  26. Maximal Matches • Maximal matching algorithms are widely used in industry (especially algorithms based on WFA and iSLIP). • PIM and iSLIP are rarely run to completion (i.e. they are sub-maximal). • We will see that a maximal match with a speedup of 2 is stable for non-uniform traffic. 048866 – Packet Switch Architectures

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