ERL Differential Current System Status
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ERL Differential Current System Status Peter Cameron with contributions from Michelle Wilinski and Christophe DeFrance (Bergoz) 17 Sep 07. Outline Damage threshold estimate Test setup pictures, block diagram,… DSA measurements Noise floor and DC drift Effect of temperature

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Outline damage threshold estimate test setup pictures block diagram dsa measurements

ERL Differential Current System StatusPeter Cameronwith contributions from Michelle Wilinski and Christophe DeFrance (Bergoz)17 Sep 07


Outline damage threshold estimate test setup pictures block diagram dsa measurements

Outline

  • Damage threshold estimate

  • Test setup pictures, block diagram,…

  • DSA measurements

    • Noise floor and DC drift

    • Effect of temperature

    • Conclusions from DSA measurements

  • FPGA measurements

    • Block diagram

    • measurement sensitivity

  • Discussion, conclusions,…


  • Outline damage threshold estimate test setup pictures block diagram dsa measurements

    1 uA-sec (6x1012 electrons, or 1uC)

    used in the following slides


    Outline damage threshold estimate test setup pictures block diagram dsa measurements

    Agilent

    FFT box

    Floppy

    Bergoz

    Electronics

    Excel

    scope

    FPGA

    board

    ethernet

    Bergoz

    Electronics

    LabVIEW

    signal

    generator

    Test Setup Block Diagram


    Outline damage threshold estimate test setup pictures block diagram dsa measurements

    Full span (PCT nominal BW is 10KHz) noise spectrum

    not 1/f !!!


    Outline damage threshold estimate test setup pictures block diagram dsa measurements

    Comparison of single toroid and difference spectra

    single toroid

    No averaging

    difference of the two toroids


    Outline damage threshold estimate test setup pictures block diagram dsa measurements

    Comparison with Bergoz measurement

    Bergoz – 5 averages (note log scale)


    Outline damage threshold estimate test setup pictures block diagram dsa measurements

    400Hz BW noise spectra

    Include spectral shaping in null?


    Outline damage threshold estimate test setup pictures block diagram dsa measurements

    Bergoz – 5 averages (note log scale)


    Outline damage threshold estimate test setup pictures block diagram dsa measurements

    Effect of temperature stabilization


    Outline damage threshold estimate test setup pictures block diagram dsa measurements

    Time/temperature dependence of difference current

    Out of office

    ~0.1 nA-sec drift

    over 160 minutes

    .01667 uA-sec

    on 1 minute

    What happened here???

    B field change?

    100uA/gauss gives .02 gauss


    Outline damage threshold estimate test setup pictures block diagram dsa measurements

    Zoom on previous slide

    .0033 uA-sec


    Outline damage threshold estimate test setup pictures block diagram dsa measurements

    Conclusions from DSA Measurements

    • Toroids meet Bergoz spec in uncontrolled conditions (temperature, magnetic field) of office test environment

    • Study and optimize proper thermal shielding

    • Frequent null calibration should not be needed

    • Slow loss limit should be in the range of 1nA-sec or better

    • Should be a useful diagnostic

      • Machine protection

      • (unprecedented and essential) Halo studies at ~10-6need moveable scrapers?

    • Need to understand vector averaging (more on this later)


    Outline damage threshold estimate test setup pictures block diagram dsa measurements

    Outline

    • Damage threshold estimate

    • Test setup pictures, block diagram,…

    • DSA measurements

      • Noise floor and DC drift

      • Effect of temperature

      • Conclusions from DSA measurements

  • FPGA measurements

    • Block diagram

    • measurement sensitivity

  • Discussion, conclusions,…


  • Bpm also fct dcct blm block diagram

    BPM (also FCT, DCCT, BLM,…) Block Diagram


    Outline damage threshold estimate test setup pictures block diagram dsa measurements

    Test Setup Block Diagram

    ML403

    Bergoz

    Electronics

    FPGA wrapper

    A

    to

    D

    Simulink

    Signal processing, feedback loop, MPS interface,…

    ethernet

    Lab VIEW

    Bergoz

    Electronics

    DIO

    signal

    generator

    DAC

    null

    MPS

    MPS function runs independent of Control System - robustness


    Outline damage threshold estimate test setup pictures block diagram dsa measurements

    Process Variables

    (machine mode,

    beam mode,…)

    Process Variables

    (beam position,…)

    BPM Module

    Embedded processor

    running

    vXworks/EPICS

    A/D

    FPGA

    PUE signals

    x4 or x8

    1 sec event

    Beam permit

    Laser

    pre-trigger

    9.38MHz RF

    reference


    Outline damage threshold estimate test setup pictures block diagram dsa measurements

    FPGA board control panel


    Outline damage threshold estimate test setup pictures block diagram dsa measurements

    spectral content of simulated beam loss


    Outline damage threshold estimate test setup pictures block diagram dsa measurements

    Next slide is zoom on this


    Outline damage threshold estimate test setup pictures block diagram dsa measurements

    FPGA-based beam loss measurement (S/N ~same for DSA and FPGA)

    1 uA-sec loss signal

    no loss signal

    0 1 2 3 4 5 6 7 8 9 10

    Time [minutes]


    Comments conclusions

    Comments, conclusions

    • Consider toroid upgrades for RHIC

      • Present DCCTs are 5uA/rtHz?

      • Going to 0.1uA/rtHz would give much more sensitive diagnostic for machine tuning - this is important!

    • Implementation of DI measurement on FPGA board was straightforward ~2 man-weeks of Joe Mead, 1 man-week of Pete Cameron

    • Paradox? need to understand vector averaging,… see simulation

    • Where from here?

      • Basic system functionality and spec demonstrated

      • I’m on travel for most of the coming month, then Run 8

      • Priority shift to BPM electronics

    • BPM system

      • Libera demo box due in any day now (after 3 months of trying to get it)

      • I’m at ITech (Slovenia) next week to work out details of Libera in ERL

      • Commercial vendor (the major supplier of demo boards) exploring design and fab of COTS FPGA board to our spec (~$1K vs ~$10K or more for Libera box, and much simpler)

      • Joe Mead is fabbing 4ch fast digitizer mezzanine for ML403

    Hold off on further DI development until next spring?


    Suggestions for upcoming meeting agendas

    Suggestions for upcoming meeting agendas

    • Sep 17th – presentation and discussion of DCCT and differential current status

    • Sep 24th– presentation and discussion of Profile status

    • Oct 1st – presentation and discussion of BPM status

    • Oct 8th – Scrapers and collimators


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