4 bit full adder with ripple carry
Download
Skip this Video
Download Presentation
4-bit Full-Adder With Ripple Carry

Loading in 2 Seconds...

play fullscreen
1 / 15

4-bit Full-Adder With Ripple Carry - PowerPoint PPT Presentation


  • 534 Views
  • Uploaded on

4-bit Full-Adder With Ripple Carry . Adrian Corona Tuessia Ly Ali N. Warriach Advisor: Dave Parent Dec. 6, 2004. Agenda. Abstract Introduction Why Simple Theory Back Ground information (Lit Review) Summary of Results Project (Experimental) Details Results Cost Analysis Conclusions.

loader
I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
capcha
Download Presentation

PowerPoint Slideshow about '4-bit Full-Adder With Ripple Carry ' - jaden


An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript
4 bit full adder with ripple carry

4-bit Full-Adder With Ripple Carry

Adrian Corona

Tuessia Ly

Ali N. Warriach

Advisor: Dave Parent

Dec. 6, 2004

agenda
Agenda
  • Abstract
  • Introduction
    • Why
    • Simple Theory
    • Back Ground information (Lit Review)
  • Summary of Results
  • Project (Experimental) Details
  • Results
  • Cost Analysis
  • Conclusions
abstract
Abstract
  • We attempted to design a 4-bit Full Adder with Ripple carry that operated at 200 MHz and uses less than 23W/cm2 of Power and occupied an area of 295x68mm2
introduction
Introduction
  • Ripple Carry Full Adders are foundation for other logics.
  • It serves as a basic tool for Carry Look Ahead adders which are used for MSI adders and ALUs.
project details
Project Details
  • Hand Calculations
  • Cell based technique

- Built and created each layout of 1-bit separately and tested LVS.

  • Final Schematic
  • Final Layout
  • Final Simulation
cost analysis
Cost Analysis
  • Time spent on each phase of the project
    • Verifying logic = 3 hours
    • Verifying timing = 12 hours
    • Layout = 20 hours
    • Post extracted timing = 4 hours
lessons learned
Lessons Learned
  • Get extremely familiar with the Cadence tool.
  • Plan ahead and stay on schedule.
  • Get professor’s advice more often.
summary
Summary
  • Our design of 4-bit Full Adder with Ripple Carry is a building block for Carry Look Ahead adder which can further be used for MSI adders and ALUs.
  • We were successful in proving that our design works without the Flip Flops.
  • In future we think its better to work with the Carry Look Ahead adder instead.
acknowledgements
Acknowledgements
  • Thanks to our significant others for bearing our time away from home.
  • Thanks to Cadence Design Systems for the VLSI lab
  • Thanks to Synopsys for Software donation
  • Thanks to Dr. Parent for his patience and valuable lessons.
ad