4 bit full adder with ripple carry
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4-bit Full-Adder With Ripple Carry . Adrian Corona Tuessia Ly Ali N. Warriach Advisor: Dave Parent Dec. 6, 2004. Agenda. Abstract Introduction Why Simple Theory Back Ground information (Lit Review) Summary of Results Project (Experimental) Details Results Cost Analysis Conclusions.

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4-bit Full-Adder With Ripple Carry

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4 bit full adder with ripple carry

4-bit Full-Adder With Ripple Carry

Adrian Corona

Tuessia Ly

Ali N. Warriach

Advisor: Dave Parent

Dec. 6, 2004


Agenda

Agenda

  • Abstract

  • Introduction

    • Why

    • Simple Theory

    • Back Ground information (Lit Review)

  • Summary of Results

  • Project (Experimental) Details

  • Results

  • Cost Analysis

  • Conclusions


Abstract

Abstract

  • We attempted to design a 4-bit Full Adder with Ripple carry that operated at 200 MHz and uses less than 23W/cm2 of Power and occupied an area of 295x68mm2


Introduction

Introduction

  • Ripple Carry Full Adders are foundation for other logics.

  • It serves as a basic tool for Carry Look Ahead adders which are used for MSI adders and ALUs.


Project details

Project Details

  • Hand Calculations

  • Cell based technique

    - Built and created each layout of 1-bit separately and tested LVS.

  • Final Schematic

  • Final Layout

  • Final Simulation


Longest path calculations

Longest Path Calculations


Schematic

Schematic


Layout

Layout


Layout w o ff

Layout w/o FF


Verification

Verification


Simulations

Simulations


Cost analysis

Cost Analysis

  • Time spent on each phase of the project

    • Verifying logic = 3 hours

    • Verifying timing = 12 hours

    • Layout = 20 hours

    • Post extracted timing = 4 hours


Lessons learned

Lessons Learned

  • Get extremely familiar with the Cadence tool.

  • Plan ahead and stay on schedule.

  • Get professor’s advice more often.


Summary

Summary

  • Our design of 4-bit Full Adder with Ripple Carry is a building block for Carry Look Ahead adder which can further be used for MSI adders and ALUs.

  • We were successful in proving that our design works without the Flip Flops.

  • In future we think its better to work with the Carry Look Ahead adder instead.


Acknowledgements

Acknowledgements

  • Thanks to our significant others for bearing our time away from home.

  • Thanks to Cadence Design Systems for the VLSI lab

  • Thanks to Synopsys for Software donation

  • Thanks to Dr. Parent for his patience and valuable lessons.


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