Group3 no more counting of literals
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Subramanian Iyer Satrajit Chatterjee Ajit Pal Yinghua Li Pawel Kerntopf Donald Chai Dennis Wu Leyla Nazhandali Ingmar Neumann Babette Van Antwerpen Alan Mishchenko. Michael Theobald Victor Kravetz Yunjian Jiang Aiqun Cao Jordi Cortadella Jackie Rice Jean-Christoph Madre

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Group3: No more counting of Literals

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Group3 no more counting of literals

Subramanian Iyer

Satrajit Chatterjee

Ajit Pal

Yinghua Li

Pawel Kerntopf

Donald Chai

Dennis Wu

Leyla Nazhandali

Ingmar Neumann

Babette Van Antwerpen

Alan Mishchenko

Michael Theobald

Victor Kravetz

Yunjian Jiang

Aiqun Cao

Jordi Cortadella

Jackie Rice

Jean-Christoph Madre

Timothy Kam

Christian Stangier

Charles Brej

Dmitri Maslov

Group3: No more counting of Literals


When why we count literals

When/Why We Count Literals

  • Multi-level combinational logic optimization

    • LC is sum of literals of all nodes in network

    • Different flavours of LCs

  • Delay independent logic factorization

  • Don’t care optimization

  • Objective is to minimize LC

    • Used to correlate well with circuit area


Problems

Problems

  • Factorization can have negative effects on

    • Delay

      • Creates additional levels of logic, higher fanouts

    • Area

      • Can result in larger area after technology mapping (e.g. tree based mapper)

      • Can increase congestion, wire length

    • Power

      • Logic duplication can reduce power


Problems contd

Problems (contd.)

  • No correlation between LC and area, delay and power.

  • Logic optimization happens quite late in synthesis process

    • Earlier optimizations may create problems that cannot be fixed at this stage

    • Blame the other guy!


Directions

Directions

1. Identify cost vectors that correlate with objective functions

  • Should capture:

    • Structural regularities

    • Local communications

    • Wire length, congestion

  • Efficient to compute

  • Need access to real circuits

    2. Develop algorithms


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