CMP Modeling and DFM
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AMC-2008 Invited Talk September 23, 2008 Andrew B. Kahng, UCSD Kambiz Samadi, UCSD PowerPoint PPT Presentation


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CMP Modeling and DFM. AMC-2008 Invited Talk September 23, 2008 Andrew B. Kahng, UCSD Kambiz Samadi, UCSD Rasit O. Topaloglu, AMD [email protected] http://vlsicad.ucsd.edu. Step height. Over-removal. Puddling. Dishing. Erosion. CMP Process.

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AMC-2008 Invited Talk September 23, 2008 Andrew B. Kahng, UCSD Kambiz Samadi, UCSD

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Amc 2008 invited talk september 23 2008 andrew b kahng ucsd kambiz samadi ucsd

CMP Modeling and DFM

AMC-2008 Invited Talk

September 23, 2008

Andrew B. Kahng, UCSD

Kambiz Samadi, UCSD

Rasit O. Topaloglu, AMD

[email protected]://vlsicad.ucsd.edu


Cmp process

Step height

Over-removal

Puddling

Dishing

Erosion

CMP Process

  • Post-CMP wafer topography depends on metal density, individual feature widths and spacings

    • Long-range and short-range phenomena

  • Design manuals specify acceptable metal density ranges

  • “Dummy” fills inserted to make layout density more uniform

    • Else, CMP-related problems…

slurry

  • Contains abrasives and chemicals

conditioner

  • A disk with diamond pyramids

  • Improves removal rate

pad

wafer


Beol contribution to variation ibm

BEOL Contribution to Variation (IBM)


Agenda

Agenda

CMP fill, DFM, and design-awareness

Example questions

Opportunities for design-driven fill

What is still left on the table

Recap


Cmp and design for manufacturability

CMP and Design for Manufacturability

Design Timing

and Power

R,C Parasitics

Topography

Lithographic

Manufacturability

Depth of Focus

CMP

  • CMP and Fill effects

    • Cu erosion and dishing change resistance

    • Fill helps planarity but changes capacitance

    • Topographic variation translates to focus variation for imaging of subsequent layers

    •  process window  linewidth variation  R, C variation

  • CMP impacts both IC parametrics and manufacturability


The cmp fill insertion problem

The CMP Fill Insertion Problem

  • Given

    • A grid

    • A fill size

    • Number of fills to be inserted

      to meet target density

  • Output

    • Fill configuration that minimizes

      intra- and inter-layer coupling

X% improvement

Interconnect Coupling (F)


Current cmp fill insertion approach

Current CMP Fill Insertion Approach

  • Layout density verified in fixed-size “windows”

  • Primitive fill insertion methods – e.g.:

    • Intersect array of potential fill shapes with empty space

    • Adjust sizes and spacings, or iteratively execute a ‘multi-pass’ heuristic, to improve density variation and reduce the number of fill shapes

  • Handled by either design house or foundry


Optimizers have improved 1998 present

Optimizers Have Improved (1998-present)

  • Global optimization with millions of variables in large linear program – Kahng et al. 1998)

    • Optimization outcome very well-behaved

  • “Difficult” image sensor chip


Pre post fill densities

Pre-/Post- Fill Densities

Original Density Histogram (DD = 31%)

minFill

Density Histogram

(DD = 15%)

minVar Density Histogram

(DD = 13%)


Existing cmp fill insertion approach

Existing CMP Fill Insertion Approach

Layout density checked in fixed-size “windows”

Primitive fill insertion methods – e.g.:

Intersect array of potential fill shapes with empty space

Adjust sizes and spacings, or iteratively execute a ‘multi-pass’ heuristic, to improve density variation and reduce the number of fill shapes

Handled by either design house or foundry

Key issue: fill impact on timing, noise, power

Intralayer coupling: keep-off design rule defines minimum spacing between fill and interconnect

Larger keep-off  less performance impact, but worse density control, more variation and performance impact…

Smaller keep-off  better density control and less variation, but more capacitance, performance impact…

Conflicting goals !!!

Interlayer coupling: no design rules

Key word: “design”


What do we want

What Do We Want?

  • Objective forManufacturability = Minimum Variation

    subject to upper bound on window density

  • Objective forDesign = Minimum Fill

    subject to upper bound on window density variation

For Manufacturability at 65nm and below:

  • Multiple relevant planarization length scales: control density at multiple window sizes

  • N-layer BEOL stack: control density in a multi-layer sense

  • Coupling, etch, OPC etc.: provide “staggered” fill patterns or wire-like (“track”) fill

  • Mechanical stability in low-k: achieve (maximal) via fill

  • Better CMP modeling: achieve smoothness of density

  • Analog and mixed-signal variability: symmetric fill

  • … all within a CMP model-driven framework


Example of symmetric fill analog regions

Analog Cell

Axis of Symmetry

Example of Symmetric Fill (Analog Regions)


Also want design driven fill

Layout, Design Data, Fill Constraints

“Intelligent” Fill

Internal CMP Model

Uniform Effective Density +Step Height Objective

Post-Fill Layout, Reports

Signoff CMP Model

Also Want Design-Driven Fill

  • Global optimization

  • CMP model-driven fill synthesis

    • Must tightly couple CMP model to parasitic extraction and timing analysis engines

    • Efficiency of design flow is an issue  internal CMP model vs. signoff CMP model

  • Design-driven fill synthesis

    • Design concerns: timing, signal integrity, power

    • Concurrent analysis of fill impact on both topography and timing

    • New optimizations possible

      • Trade OPC cost for variability ?

      • Good design practices rewarded by reduced BEOL guardband in design ?

      • Fix hold time violations by inserting extra fill ?


Example timing aware fill

Example: Timing-Aware Fill

  • General guidelines

    • Minimize total number of fill features

    • Minimize fill feature size

    • Maximize space between fill features

    • Maximize buffer distance between original and fill features

  • Sample observations in literature

    • Motorola [Grobman et al., 2001]: key parameters are fill feature size and keep-out distance

    • Samsung [Lee et al., 2003]: floating fills must be included in chip-level RC extraction and timing analysis to avoid timing errors

    • MIT MTL [Stine et al., 1998]: rule-based area fill methodology to minimize added interconnect coupling capacitance

  • Not a new concept, but only now reaching production design flows


M2 timing aware keepout

M2 Timing-Aware Keepout


Critical net flow timing power aware

Critical-Net Flow (Timing-, Power-Aware)


Example questions design flow

Example Questions (Design Flow)

  • Is CMP fill impact on dynamic power (CV2f) large enough to worry about?

  • Can CMP fill meaningfully improve timing robustness ?

    • Shortcut power/ground distribution networks with grounded fill  less IR drop ?

    • Use fill to add extra capacitance to hold time critical paths  more robust timing ? (And, additional decoupling cap?)

  • What good layout design practices correspond to (can be incented by) reduced RC extraction guardband?

  • How tightly must CMP modeling be integrated into the design flow ?

    • Which tool (placer, router, physical verification, …) owns the CMP-related signoffs of performance and manufacturability ?


Example questions cmp modeling

Example Questions (CMP Modeling)

What layout parameters must be comprehended by a CMP model?

  • Calibration data for each grid point:

  • X (um), Y (um)

  • Density

  • Cu thickness (A)

  • Dielectric thickness (A)

  • Optional: Pre-CMP Cu thickness, trench depth, barrier thickness, etc.

Test Layouts

Signoff CMP Model

(or silicon)

Layout, Design Data, Fill Constraints

Topography Predictions

(or measurements)

Intelligent Fill

Approximation of Signoff CMP Model

Internal CMP Model

Uniform Effective Density +Step Height Objective

How do we achieve a CMP model that is optimizable (fast, simple, accurate, …)?

Post-Fill Layout, Reports

Signoff CMP Model

Are CMP processes and models stable enough to drive design flows?


Example questions manufacturing closure

Example Questions (Manufacturing Closure)

  • Side view showing thickness variation over regions with dense and sparse layout.

  • Top view showing CD variation when a line is patterned over a region with uneven wafer topography, i.e., under conditions of varying defocus.

How tightly do we need to connect OPC to post-CMP topography simulation ?

What fill patterning strategies offer the best variability – mask cost tradeoff ?


Agenda1

Agenda

CMP fill, DFM, and design-awareness

Example questions

Opportunities for design-driven fill

What is still left on the table

Recap


Design timing aware fill

Design- (Timing)-Aware Fill

keep-off distance

  • Preserves performance while addressing density objectives

  • Shown: avoidance of fill on same/adjacent layers near a critical net

  • Timing-driven place & route creates natural “victims” for fill insertion when it leaves extra space around a critical net !

  • Other issues: OPC, data volume, …


What we leave on the table an example

What We Leave on the Table: An Example

  • More sophisticated pattern synthesis guidelines exist but have not been automated

  • Want automation

  • Want to account for circuit timing in fill insertion

  • Want to account for interlayer coupling impact on timing

  • Want to gain back the capacitance increase introduced by timing-unaware (traditional) fills

  • Want power-aware fill for power-critical circuits

  • Next few slides: an ‘energy model’ heuristic for fill pattern synthesis

  • Example: Place fills to form a hour-glass shape

  • Minimize number of fills close to interconnects

  • Place fills away from interconnects.


Adaptive region definition

Adaptive Region Definition

  • Region-based instead of window-based fill insertion

  • Maximum-width empty regions identified between facing interconnects, using scanline algorithm

  • After stripping out keep-off distances, a grid holding possible fill locations is formed

  • If orthogonal interconnect segments exist, disable overlapping grid rectangle locations

Interconnect

Region

Grid rectangle

Keep-off distance


The grid model utilizing bonds

The Grid Model Utilizing Bonds

  • In this example, there are 36 rectangles with two fills in the grid shown below

  • An auxiliary frame is formed holding grid rectangles with bonds in between

  • Each bond has an adjustable energy

    • Originally considered physical analogy of electrons filling orbits…

  • When inserting a fill, bonds incident to a rectangle are summed up to find an energy; we find a minimum energy location to insert a fill

Bonds incident to a location

Region

Grid rectangle

Interconnect

Keep-off distance

Vertical bond

Fill

Horizontal bond

Auxiliary frame


Energy modeling in a grid

Energy Modeling in a Grid

  • Modeling of bonds indicates which location should be filled with higher priority

  • Model is flexible enough to satisfy target guidelines

  • Adjustable four-parameter model for vertical and horizontal bonds

    • Although we use linear models, second-order and more complex models can also be used

  • Z axis gives the bond energy.

Vertical model:

Y

Horizontal model:

i : enumeration for a row of grid rectangle locations

j : enumeration for a column of grid rectangle locations

imid : middle row number

jmid : middle column number

,,, : fitting parameters

X

Energies for vertical bonds

Energies for horizontal bonds


Experimental setup and protocol

Experimental Setup and Protocol

  • Cadence SOC Encounter v5.2 used for placement and clock tree synthesis and NanoRoute used for routing

  • Synopsys StarRCXT 2006.06 used for RC extraction

  • C++ code for proposed fill insertion methodology MFO (Metal Fill Optimizer).

  • Comparison against best available industry tools : Mentor Calibre, Blaze IF

  • TSMC 65nm GPlus library

  • S38417, AES, ALU and an industrial (microprocessor) testcase

  • Compare impact of fill algorithm on timing and power

Fill Design Rules from Library Exchange File

Sizes for Traditional Fill


Interlayer aware fill synthesis flow

Interlayer-Aware Fill Synthesis Flow

  • Add vertical bonds

Slack Comparison


Power aware fill

Power-Aware Fill

  • Alter flow to handle interconnect switching power criticality

  • Place, synthesize clock network and route design

  • Extract SPEF parasitics from DEF

  • Compute interconnect switching power using SPEF file from Step 2

  • Use Perl scripts to obtain top power-critical net names

  • Check critical nets on neighboring layers for each net

  • Update energy values for bonds

  • Insert power-aware fills


Timing slack results

Timing Slack Results

  • Timing slacks shown

  • Less negative (towards the right) is better

  • Proposed Metal Fill Optimizer (MFO) outperforms intelligent fill (IF) variations


Post fill topographies and histograms

Post-Fill Topographies and Histograms

  • Core1 of industrial testcase

Traditional fill

MFO fill

  • We obtain a histogram with a single peak


Agenda2

Agenda

CMP fill, DFM, and design-awareness

Example questions

Opportunities for design-driven fill

What is still left on the table

Recap


Recap what s on the table

Recap: What’s on the Table

  • Example of a physically-motivated, simple heuristic

  • Testbed with 65GP process and fill design rules, leading-edge commercial tools

  • Automation of fill insertion guidelines and intuitions

  • Large testcases including an industrial (uP) testcase

  • Interlayer layout awareness utilized for first time

  • Timing-aware and power-aware fill options

  • Can reduce fill impact on timing

    • by up to 85% for 30% pattern density

    • by up to 65% for 60% pattern density

  • Significant value is left on the table by today’s CMP fill methodologies


Recap example open questions

Recap: Example Open Questions

Design Flow

Is CMP fill impact on dynamic power (CV2f) large enough to worry about?

Can CMP fill meaningfully improve timing robustness ?

Can good (layout) design practices correspond to (can be incented by) reduced RC extraction guardband ?

How tightly must CMP modeling be integrated into the design flow ?

CMP Modeling

Which layout parameters are necessary to feed a CMP model?

How do we achieve a CMP model that is optimizable (fast, simple, accurate, …)?

Are CMP processes and models stable enough to drive design flows?

Manufacturing Handoff

How tightly do we need to connect OPC to post-CMP topography simulation ??

What fill patterning strategies offer the best variability – mask cost tradeoff ?


Amc 2008 invited talk september 23 2008 andrew b kahng ucsd kambiz samadi ucsd

Thank you!


Religious questions in beol dfm

Religious Questions in BEOL DFM

  • Should CMP fill be owned by the routing / timing closure tool or by the DRC / PG tool?

    • Answer: proper fill is best achieved today post-layout by a tool that maintains the signoff

  • Must fill be “timing-driven”, or is “timing-aware” sufficient?

    • Answer: “Timing-aware” is likely sufficient through the 45nm node

  • Are CMP and litho simulations for “more accurate parasitics and signoff” really necessary?

    • Answer: Probably not. CDs and thickness variations are “self-compensating” w.r.t. timing. Guardbands are reasonable. There is a big mess with existing calibrations of the RC extraction tool to silicon.

  • If two solutions both meet the spec, are they of equal value?

  • How elaborate must cost functions and layout knobs be for EDA tools to understand via yield / reliability, EM, etc.?

  • ...


Intelligent fill goals for 65nm and beyond

“Intelligent” Fill Goals for 65nm and Beyond

  • True timing- and SI-awareness

    • Driven by internal engines for incremental extraction, delay calculation, static timing/noise analysis

    • Open Question: is this done by the router? Or post-layout processing?

  • True multi-layer, multi-window global optimization of effective density smoothness and uniformity

    • Recall: millions of “tiles” – can we optimize all fill on all layers simultaneously?

  • Analog fill, capacitor fill, via fill

  • Floating, grounded and track fill

  • Standalone, ECO, and ripup-refill use models

  • Supports thickness bias models (CMP predictors)

  • Key technology for managing BEOL variability and enhancing parametric yield


Conclusions futures for cmp fill in dfm

Conclusions: Futures for CMP/Fill in DFM

  • Goal: Design convergence

    • Integrate design intent and physical models

    • CMP simulation + fill pattern synthesis + RCX + timing/SI driven

  • Performance awareness

    • Maintain timing and SI closure

    • “Multi-use” fill: IR drop management, decap creation

    • Device layer: STI CMP modeling / fill synthesis, etch dummy

  • Topography awareness

    • Close the loop back to RCX, fill pattern synthesis, OPC guidance

  • Intelligent fill pattern synthesis

    • Minimum variation and smoothness in addition to density bounds

    • Handle MANY constraints at once: multi-window, multi-layer, etc.

    • Optional mixing of grounded and floating fill

    • Mask data volume control (e.g., shot-size aware, compressible fill)


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