Accurate clock mesh sizing via sequential quadratic programming
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Accurate Clock Mesh Sizing via Sequential Quadratic Programming. Venkata Rajesh Mekala, Yifang Liu, Xiaoji Ye, Jiang Hu, Peng Li Department of ECE, Texas A&M University From ISPD’10. Systematic way - Sequential Quadratic Programming (SQP).

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Accurate clock mesh sizing via sequential quadratic programming

Accurate Clock Mesh Sizing via Sequential Quadratic Programming

Venkata Rajesh Mekala, Yifang Liu, Xiaoji Ye, Jiang Hu, Peng Li

Department of ECE, Texas A&M University

From ISPD’10


Systematic way sequential quadratic programming sqp
Systematic way - Sequential Quadratic Programming (SQP) Programming

  • One of the most popular and robust algorithms for nonlinear continuous optimization

  • Mathematical theory based


Definitions about sqp
Definitions about SQP Programming

  • Original problem

  • Lagrangian function

  • Jacobian


Optimality condition in one dimensional problem
Optimality condition in one dimensional problem Programming

  • Optimal solution will exist in f’(x)=0 and f’’(x)>0


Optimality condition in sqp
Optimality condition in SQP Programming

  • Karush-Kuhn-Tucker (KKT) conditions

  • Second order optimality condition

    is positive definite

    H means Hessian matrix


How to solve
How to solve? Programming

  • In one dimensional problem

    • Newton’s method

  • In SQP


Result in qp form
Result in QP form Programming


Outline
Outline Programming

  • Introduction

  • Problem formulation

  • SQP for clock network sizing

  • Sensitivity analysis

  • Algorithm overview

  • Experimental results and Conclusions


Introduction
Introduction Programming

  • Why clock mesh?

    • Uniform, low skew clock distribution

    • Better tolerance to On-Chip Variation (OCV)


Introduction cont
Introduction (cont.) Programming

  • Disadvantages

    • Larger area (metal resources)

    • Higher power consumption

    • Sophisticated delay model is hard to analyze highly coupled structure


Previous works
Previous works Programming

  • Using clock tree networks

    • Moment-based sensitivity analysis

      • restricted in clock tree

    • SQP under a power budget

      • Inaccurate

    • Divide and Conquer using SLP

      • applies only to clock tree


Previous works cont
Previous works (cont.) Programming

  • Using non-clock tree networks

    • Crosslinks

      • difficult to extend to a mesh

    • Clock mesh


Our contributions
Our Contributions Programming

  • Adopt a current-source based gate modeling approach to speed up the accurate analysis

  • Develop efficient adjoint sensitivity analysis to provide desirable info

  • First clock mesh sizing using systematic solution search and accurate delay model


Problem formulation
Problem formulation Programming

  • Given a CDN consisting of a clock mesh driven by a clock tree

  • Minimize power consumption while meeting skew constraints by sizing the mesh

  • Power dissipation is approximated by mesh area

  • Skew is presented in a delay variance form


Formulae and terms
Formulae and terms Programming

  • I: set of interconnect in the mesh

  • xi: size of element i

  • wi: area of ith element

  • S: set of sinks

  • Dj: propaagation delay from clock tree root to sink j


Model of a clock mesh
π Programming model of a clock mesh


Sqp for clock network sizing
SQP for clock network sizing Programming

  • Use QP solver to solve


Quasi newton approximation of hessian
Quasi-Newton approximation of Hessian Programming

  • Using BFGS method

    where



Linearize the original circuit
Linearize the original circuit Programming

  • Using linearized compact gate model

  • Kirchhoff CL

    and VL


Algorithm overview
Algorithm overview Programming


Experimental results
Experimental results Programming

  • The benchmarks are taken from ISPD and ISCAS. The BPTM 65-nm technology transistor models have been used


Table of results
Table of results Programming



Runtime of cmssqp
Runtime of CMSSQP Programming


Conclusions
Conclusions Programming

  • Can easily extend for sizing buffers and mesh element simultaneously

  • Achieve up to 33% area reduction

  • Robust in dealing with any complex clock mesh network


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