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Accurate Clock Mesh Sizing via Sequential Quadratic Programming. Venkata Rajesh Mekala, Yifang Liu, Xiaoji Ye, Jiang Hu, Peng Li Department of ECE, Texas A&M University From ISPD’10. Systematic way - Sequential Quadratic Programming (SQP).

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Accurate Clock Mesh Sizing via Sequential Quadratic Programming

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## Accurate Clock Mesh Sizing via Sequential Quadratic Programming

Venkata Rajesh Mekala, Yifang Liu, Xiaoji Ye, Jiang Hu, Peng Li

Department of ECE, Texas A&M University

From ISPD’10

### Systematic way - Sequential Quadratic Programming (SQP)

• One of the most popular and robust algorithms for nonlinear continuous optimization

• Mathematical theory based

• Original problem

• Lagrangian function

• Jacobian

### Optimality condition in one dimensional problem

• Optimal solution will exist in f’(x)=0 and f’’(x)>0

### Optimality condition in SQP

• Karush-Kuhn-Tucker (KKT) conditions

• Second order optimality condition

is positive definite

H means Hessian matrix

### How to solve?

• In one dimensional problem

• Newton’s method

• In SQP

### Outline

• Introduction

• Problem formulation

• SQP for clock network sizing

• Sensitivity analysis

• Algorithm overview

• Experimental results and Conclusions

### Introduction

• Why clock mesh?

• Uniform, low skew clock distribution

• Better tolerance to On-Chip Variation (OCV)

### Introduction (cont.)

• Larger area (metal resources)

• Higher power consumption

• Sophisticated delay model is hard to analyze highly coupled structure

### Previous works

• Using clock tree networks

• Moment-based sensitivity analysis

• restricted in clock tree

• SQP under a power budget

• Inaccurate

• Divide and Conquer using SLP

• applies only to clock tree

### Previous works (cont.)

• Using non-clock tree networks

• difficult to extend to a mesh

• Clock mesh

### Our Contributions

• Adopt a current-source based gate modeling approach to speed up the accurate analysis

• Develop efficient adjoint sensitivity analysis to provide desirable info

• First clock mesh sizing using systematic solution search and accurate delay model

### Problem formulation

• Given a CDN consisting of a clock mesh driven by a clock tree

• Minimize power consumption while meeting skew constraints by sizing the mesh

• Power dissipation is approximated by mesh area

• Skew is presented in a delay variance form

### Formulae and terms

• I: set of interconnect in the mesh

• xi: size of element i

• wi: area of ith element

• S: set of sinks

• Dj: propaagation delay from clock tree root to sink j

### SQP for clock network sizing

• Use QP solver to solve

### Quasi-Newton approximation of Hessian

• Using BFGS method

where

### Linearize the original circuit

• Using linearized compact gate model

• Kirchhoff CL

and VL

### Experimental results

• The benchmarks are taken from ISPD and ISCAS. The BPTM 65-nm technology transistor models have been used

### Conclusions

• Can easily extend for sizing buffers and mesh element simultaneously

• Achieve up to 33% area reduction

• Robust in dealing with any complex clock mesh network