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Digital Logic. Abstract.

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abstract
Abstract

The basics of Boolean algebra will be introduced, starting from simple combinational logic functions and basic sequential logic circuits such as latches and flip-flops. Based on these fundamentals, more complex logic structures such as decoders, adders, registers, and memories will constructed and their performance analyzed. FET Transistor basics will be reviewed and circuits introduced that demonstrate implementations of the basic logic elements in CMOS technology. The logic functions used as the architectural basis for programmable devices used in spaceborne electronics will be examined and analyzed.

Some common design problems found in flight circuits will be introduced.

logic outline
Logic Outline
  • Introduction
  • Basic Logic
  • Hardware
  • Combinational Logic
  • Sequential Logic
logic values
Logic Values
  • For real binary hardware
    • Either a ‘1’ or a ‘0’
    • “Most of the time”
  • Other types of hardware can be have more than two values
  • Simulation can use a multi-value logic system
    • VHDL Std_Logic uses a nine-valued logic
binary hardware logic values
Binary Hardware Logic Values
  • Logic ‘1’
  • Logic ‘0’
  • Undefined value
ttl logic levels
TTL Logic Levels
  • Logic ‘1’ threshold - VIH
      •  2.0 V
  • Logic ‘1’ threshold - VIL
      •  0.8 V
  • Undefined
      • 0.8 V < v < 2.0 V
ttl logic levels examples of undefined values

Logic ‘1’

2.0V

Undefined

0.8V

Logic ‘0’

TTL Logic LevelsExamples of Undefined Values
  • Floating signals may take on illegal values
  • What happens during a signal transition?
mil std 1553
MIL-STD-1553
  • Three physical values
      • > +VTH
      • < - VTH
      • -VTH < v < +VTH
  • All values have meaning in MIL-STD-1553
intel flash memory
Intel Flash Memory
  • Intel® StrataFlash™ memory components store two bits per cell for high density and low cost.
  • Smaller margins for radiation.

Source: http://www.intel.com/design/flcomp/prodbref/298044.htm

physical logic values
Physical Logic Values
  • Magnetic field (core memory, plated wire)
  • Voltage (static CMOS logic)
  • Charge (DRAM)
  • Position (contacts open/closed)
  • Sound (tones for a modem)
  • Light (fiber optics - MIL-STD-1773)
  • Etc.
logic values13
Logic Values
  • Levels
    • \'0\' or \'1\'
  • Pulses
    • Presence or absence of pulses
    • Pulse widths
    • Number of pulses
  • Zero crossings
a multi valued logic system
A Multi-valued Logic System

TYPE std_ulogic IS (

‘U’, -- Uninitialized

‘X’, -- Forcing Unknown

‘0’, -- Forcing 0

‘1’, -- Forcing 1

‘Z’, -- High Impedance

‘W’, -- Weak Unknown

‘L’, -- Weak ‘0’

‘H’, -- Weak ‘1’

‘-’ -- Don’t Care

);

switching algebra
Switching Algebra
  • Two-valued variable from {0,1}
  • Two binary operations
    • And ( • )
    • Or ( + )
  • One unary operation
    • Not (  )
binary operation and

A B Y

0 0 0

0 1 0

1 0 0

1 1 1

Binary Operation - And
binary functions
Binary Functions
  • How many functions are there of two binary variables?
    • Basic combinatorics
    • 4 positions or rows: 00, 01, 10, 11
    • For each position you can select one of two values {0, 1}
    • Order counts since it is a function
    • Number of functions = 2 x 2 x 2 x 2 = 24 = 16
binary functions cont d
Binary Functions - cont’d
  • How many functions are there of n binary variables?
    • 2n positions or rows
      • for n = 2: 00, 01, 10, 11
      • for n = 3: 000, 001, 010, 011, 100, 101, 110, 111
    • For each position or row you can select one of two values {0, 1}
    • Number of functions = 2^2n
      • for n = 2: 22 = 4; 2 x 2 x 2 x 2 = 24 = 16
      • for n = 3: 23 = 8; 2 x 2 x 2 x 2 x 2 x 2 x 2 x 2 = 28 = 64
      • for n = 4: 24 = 16; 216 = 65536
fan in

A

Y

AND 2

B

A

B

Y

AND 3

C

A

B

Y

AND 4

C

D

Fan-In
  • Number of inputs to a logic gate
  • Examples for And function
      • n = 2: Y = A • B
      • n = 3: Y = A • B • C
      • n = 4: Y = A • B • C • D
logic functions

A

A

Y

AND 2

B

B

A

Y

A

Y

Y

OR 2

INV

B

C

A

Y

AND 2

B

D

Logic Functions
  • Any logic function can be implemented with And, Or, and Not.
  • One standard form is the sum of products
      • Example: Y = (A • B + C • D)

Inputs And gates Or gates Inverters Outputs

universal logic gate introduction
Universal Logic GateIntroduction
  • Some other logic functions
    • NOR ::= Negative OR

Y = ( A + B )´

    • NAND ::= Negative AND

Y = ( A • B )´

    • Multiplexor

Y = A • S + B • S´

    • Look up table (LUT)

Small memory

universal logic gate nor function

A

Y

A

Y

=

A

A

Y

Y

NOR 2

B

INV

A

Y

A

A

A

A

NOR 2

B

Y

=

Y

Y

AND 2

Y

B

A

B

B

Y

B

NOR 2

B

A

A

A

A

A

Y

Y

Y

=

Y

Y

NOR 2

B

B

OR 2

NOR 2

B

B

B

Universal Logic GateNOR Function
  • NOR ::= Negative OR

Y = ( A + B )´

NOT

AND

NOR 2

OR

universal logic gate nand function

A

NOT

Y

Y

A

=

Y

A

A

Y

B

NAND 2

INV

A

A

A

AND

A

A

Y

Y

Y

=

Y

Y

AND 2

B

B

B

NAND 2

NAND 2

B

B

A

Y

A

A

A

A

B

OR

NAND 2

Y

=

Y

Y

Y

B

OR 2

A

B

NAND 2

B

Y

B

B

NAND 2

Universal Logic GateNAND Function
  • NAND ::= Negative AND

Y = ( A • B )´

universal logic gate multiplexor function

A

A

B

B

A

V C C

V C C

V C C

Y

Y

S 0

Y

S 1

Y

S 1

S 0

S 1

S 0

D 0

D 0

D 0

D 1

G N D

D 1

D 1

Y

Y

Y

Y

Y

Y

M X 4

M X 4

D 2

D 2

M X 4

D 2

D 3

D 3

D 3

Y

Y

Y

G N D

G N D

G N D

Universal Logic GateMultiplexor Function
  • Multiplexor

Y = A • S + B • S´

OR

AND

NOT

universal logic gate look up table lut
Universal Logic Gate Look up table (LUT)
  • Look up table (LUT)

Small memory

NOT OR AND

A X Y A B Y A B Y

0 0 1 0 0 0 0 0 0

0 1 1 0 1 1 0 1 0

1 0 0 1 0 1 1 0 0

1 1 0 1 1 1 1 1 1

slide29

Logic Assignments and Duality

Logic Gate - Positive Logic

A B Y

0 0 0

0 1 0

1 0 0

1 1 1

0 = 0V

1 = 5V

Logic Gate and Voltage

A B Y

0V 0V 0V

0V 5V 0V

5V 0V 0V

5V 5V 5V

Logic Gate - Negative Logic

A B Y

1 1 1

1 0 1

0 1 1

0 0 0

1 = 0V

0 = 5V

Logic Gate - Negative Logic

A B Y

0 0 0

0 1 1

1 0 1

1 1 1

1 = 0V

0 = 5V

Reorder Rows

half adder

Truth Table

x y C S

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

A

X

Y

S

XOR 2

B

Y

A

Y

C

XAND 2

B

Half-Adder

Logic Equations

C = x • y

S = x  y

Schematic

full adder

Truth Table

x y z C S

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

Full-Adder

Logic Equations

C = x’yz + xy’z + xyz’ + xyz

= z • (x’y+xy’) + xy • (z+z’)

= z • (x  y) + x • y

= MAJ (x,y,z)

S = x’y’z + x’yz’ + xy’z’ + xyz

= x’yz’ + xy’z’ + x’y’z + xyz

= z’(x’y + xy’) + z(x’y’ + xy)

= z’(x  y) + z(x  y)’

= (x  y)  z

= x  y  z

adding two numbers
Adding Two Numbers
  • Many Types of Adders: Some examples:
  • Bit Serial Adder
    • Add time = n x f
  • Cascade Cascade Stages
    • Ripple carry adder
    • Add time = n x tPD
  • Carry Look Ahead Adder
    • Generate carries in parallel
    • e.g., 4-bit AM2902. Can have “look ahead” of the “look ahead” units.
full adder schematic

A

S

B

CIN

COUT

A

COUT

FULL ADDER

B

S

CIN

Full Adder Schematic
4 bit ripple carry adder

CIN

CIN

CIN

CIN

A

B

B

A

A

A

B

B

FULL ADDER

BIT 2

FULL ADDER

BIT 0

FULL ADDER

BIT 3

FULL ADDER

BIT 1

S

S

S

S

COUT

COUT

COUT

COUT

4-bit Ripple Carry Adder
slide36

Cin

A B C-out

0 0 0 “kill”

0 1 C-in “propagate”

1 0 C-in “propagate”

1 1 1 “generate”

A0

S

G

B1

P

C1 = G0 + C0 • P0

A

S

G

B

P

C2 = G1 + G0 • P1 + C0 • P0 • P1

A

S

G

B

P

C3 = G2 + G1 • P2 + G0 • P1 • P2

+ C0 • P0 • P1 • P2

A

S

G

G

B

P

P

C4 = ...

Carry Lookahead Adder (CLA)

slide37

Sample CLA Timing Analysis

  • Generate g and p: 1 gate delay
  • Generate C: 2 gate delays
  • Generate sum: 3 gate delays
  • Total: 6 gate delays
  • Total is independent of word length
negative numbers and subtraction
Negative Numbers and Subtraction
  • Several different codes for negative numbers
    • 2\'s complement
    • 1\'s complement
    • signed magnitude
    • others
  • For 2\'s complement, subtraction is implemented with the same hardware by negating the subtrahend. This is done by inverting each bit and adding one. The one can be added by setting the carry-in to the first stage equal to 1, saving an operation.
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