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Novel Wire Density Driven Full-Chip Routing for CMP Variation Control

Novel Wire Density Driven Full-Chip Routing for CMP Variation Control. Huang-Yu Chen † , Szu-Jui Chou † , Sheng-Lung Wang ‡ , and Yao-Wen Chang †. † National Taiwan University, Taiwan. ‡ Synopsys, Inc, Taiwan. Outline. CMP Introduction Previous Work

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Novel Wire Density Driven Full-Chip Routing for CMP Variation Control

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  1. Novel Wire Density Driven Full-Chip Routing for CMP Variation Control Huang-Yu Chen†, Szu-Jui Chou†, Sheng-Lung Wang‡, and Yao-Wen Chang† †National Taiwan University, Taiwan ‡Synopsys, Inc, Taiwan

  2. Outline • CMP Introduction • Previous Work • Wire-Density Driven Two-Pass Top-Down Routing • Experimental Results • Conclusion

  3. Outline • CMP Introduction • Previous Work • Wire-Density Driven Two-Pass Top-Down Routing • Experimental Results • Conclusion

  4. Cu Damascene Process • The Cu metallization (Damascene) contains two main steps: electroplating (ECP) and chemical-mechanical polishing (CMP) • ECP: deposits Cu on the trenches • CMP: removes Cu that overfills the trenches • Great interconnect performance and systematic yield loss are observed after CMP Open trenches ECP CMP

  5. CMP Process • CMP contains both chemical and mechanical parts • Chemically: abrasive slurry dissolves the wafer layer • Mechanically: a dynamic polishing head presses pad and wafer Polishing head Slurry Polishing pad Wafer Schematic diagram of CMP polisher

  6. dishing erosion dielectric metal Layout-Dependent Thickness Variations • Post-CMP topography strongly depends on underlying layout pattern density • Uneven layout density leads to metal dishing and dielectric erosion after CMP slurry polishing pad dielectric Oxide metal Pre-CMP Post-CMP

  7. dummy Layout Pattern Density Control • Foundries have set density rules and filled dummy features to improve CMP quality • Disadvantages of dummy fills: • Changes coupling capacitance of interconnects • Leads to explosion of mask data, putting heavy burdens to following time-consuming RETs • Routing considering uniform wire density helps control the layout pattern density • Avoid aggressive post-routing dummy fills wire

  8. Outline • CMP Introduction • Previous Work • Wire-Density Driven Two-Pass Top-Down Routing • Experimental Results • Conclusion

  9. Minimum Pin Density Global Routing • Cho et al. [ICCAD’06] selected paths with minimum pin density to reduce maximum wire density in global tiles • Paths with lower pin density tend to have lower wire density and can get much benefit from optimization T T p1 p1 p2 S S Select path p1 with lower pin density 2 possible 1-bend ST paths Path a with lower density

  10. Wire Density-Driven Cost Function • Li et al. [TCAD’07] set the cost function of a global tile tto guide a wire density-driven global router: 1 : capacity of t : demand of t : parameter of target density (=4 for 25% target density)

  11. Limitations • Both approaches only consider the wire density inside a routing tile • It may incur larger inter-tile density difference  results in irregular post-CMP thickness variations Density = 0.4 Density = 0.1 Post-CMP Thickness Need to minimize the density difference among global tiles

  12. Outline • CMP Introduction • Previous Work • Wire-Density Driven Two-Pass Top-Down Routing • Experimental Results • Conclusion

  13. Multilevel Routing • A modern chip may contain billions of transistors and millions of nets • Multilevel routing has been proposed to handle large-scale designs Already-routed net To-be-routed net ‧global routing ‧detailed routing ‧failed nets rerouting ‧refinement coarsening uncoarsening Λ-shaped multilevel routing

  14. G2 G2 G1 G1 G0 G0 Two-Pass Top-Down Routing Framework To-be-routed net Already-routed net uncoarsening uncoarsening high low Prerouting Stage 1st Pass Stage Intermediate Stage 2nd Pass Stage Voronoi-diagram based density critical area analysis (CAA) Planarization-aware top-down global routing Density-driven layer assignment and Delaunay-triangulation track assignment Top-down detailed routing and refinement

  15. G2 G1 G0 ? ? ? ? Over density among subregions Bottom-up routing Top-Down Routing Approach • Planarity is a long-range effect • Longer nets shall be planned first • greater impacts/determination for density • usually hard to predict paths • Bottom-up routing easily falls into local optima • over density may occur among subregions

  16. G2 G2 G1 G1 G0 G0 high low Density Analysis Prerouting To-be-routed net Already-routed net uncoarsening uncoarsening Prerouting Stage 1st Pass Stage Intermediate Stage 2nd Pass Stage Voronoi-diagram based density critical area analysis (CAA) Planarization-aware top-down global routing Density-driven layer assignment and Delaunay-triangulation track assignment Top-down detailed routing and refinement

  17. Density Critical Area Analysis (CAA) • Performs density analysis to guide following routing • Given a routing instance, we predict density hot spots based on the pin distribution by Voronoi diagrams

  18. q p Voronoi Diagram • The Voronoi diagram of a point set decomposes space into non-overlapping Voronoi cells • If a point q lies in the Voronoi cell of p, then q would be close to p than other points

  19. Observation of Voronoi Diagrams • Non-uniform distribution leads to large area variation among Voronoi cells Non-uniform distribution Uniform distribution

  20. pin density = 3 p Density Hot Spots Identification • If the Voronoi cell of a pin has more adjacent cells, density hot spots may occur around it • Define pin density of a pin p as # of adjacent Voronoi cells completely sitting inside a range from p

  21. 1 2 2 0 3 1 0 1 0 Global Tile Predicted Density • Map pin density to global tiles to guide global routing • The predicted density of a global tile t: = max{ pin density | pin locates within t } 1 2 2 2 1 1 3 2 1 1 1 Pin density Predicted density ofglobal tile

  22. G2 G2 G1 G1 G0 G0 high low 1st Pass Top-Down Global Routing To-be-routed net Already-routed net uncoarsening uncoarsening Prerouting Stage 1st Pass Stage Intermediate Stage 2nd Pass Stage Voronoi-diagram based density critical area analysis (CAA) Planarization-aware top-down global routing Density-driven layer assignment and Delaunay-triangulation track assignment Top-down detailed routing and refinement

  23. Planarization-Aware Global Routing • Objectives: • Encourage each global tile to satisfy density upper- and lower-bound rules • Minimize the density difference among global tiles 0.1 0.3 0.2 0.2 0.5 0.1 0.4 0.2 0.3 Density = 0.5 Density = 0.1 Wire density map Density = 0.2 Post-CMP Thickness

  24. Planarization-Aware Cost Function • Planarization-aware cost of global tile t with density dt: : predicted density of t (prerouting density CAA) : positive penalty (> 0) : negative reward (< 0) : average density of tiles around t : user-define parameter

  25. G2 G2 G1 G1 G0 G0 high low Intermediate Layer/Track Assignment To-be-routed net Already-routed net uncoarsening uncoarsening Prerouting Stage 1st Pass Stage Intermediate Stage 2nd Pass Stage Voronoi-diagram based density critical area analysis (CAA) Planarization-aware top-down global routing Density-driven layer assignment and Delaunay-triangulation track assignment Top-down detailed routing and refinement

  26. Density-Driven Layer Assignment • Goal: to evenly distribute segments to layers • Minimizes the panel density while balancing the local density of each layer • local density: # of segments and obstacles in a column • panel density: maximum local density among all columns Chip layout(aerial view)

  27. 3 2 s1 s2 4 3 4 3 2 o2 s6 4 3 4 3 4 3 4 4 o1 s3 4 3 4 3 s5 s4 s1 s2 1 1 s6 o2 1 3 o1 s3 3 1 3 3 s5 s4 Density-Driven Layer Partitioning • Builds horizontal constraint graphHCG(V,E) • Node: segment and obstacle • Cost of an edge (vi, vj): maximum local density of overlapping columns between vi and vj • Partitions layer groups by max-cut, k-coloring algorithms

  28. 3 2 4 3 4 4 3 s1 s2 s1 s2 1 1 1 1 s6 o2 s6 o2 1 3 3 3 o1 s3 o1 s3 3 1 1 1 3 3 3 3 s5 s4 s5 s4 Minimum-Impact Repair Procedure • For the fixed-layer obstacle which is not assigned to the correct layer • Exchanges its layer with the layer of a connected segment whose edge cost is the maximum Exchange layer of obstacle O1 with that of S6

  29. Layer 1 Layer 3 Density-Driven Layer Assignment Result

  30. Non-uniform distribution Uniform distribution Density-Driven Track Assignment • Goal: to keep segments spatially separated in a panel • Uses good properties of Delaunay Triangulation (DT) • Represents each segment by three points, two end points and one center point, and analyzes the DT • Non-uniform segment distribution  large area difference among triangles in DT

  31. su sb Artificial Segment • Model the density distribution of each neighboring panel into an artificial segmentlying on the boundary • Length: the average occupied length per track • Center: the center of gravity of all segments and obstacles

  32. su sb Delaunay-Triangulation Track Assignment • Define flexibilityof a segment si, • ti: number of assignable tracks for si • li: length of si • Insert segments in the non-decreasing order of flexibility • Each segment is assigned to the track that minimizes the area difference among all triangles of DT s1 s2 s3 1 ξ(s1) = 4+1/2 = 4.5 2 ξ(s2) = 4+1/1 = 5 3 o1 ξ(s3) = 3+1/8 = 3.125 4

  33. su sb A Density-Driven Track Assignment Example 1 s3 2 ξ(s1) = 4.5 3 o1 ξ(s2) = 4 4 1 s3 2 ξ(s1) = 4.5 3 o1 4 s2 Segment 1 s3 s1 2 Artificial segment 3 o1 4 s2 Layer 1 obstacle

  34. Outline • CMP Introduction • Previous Work • Wire-Density Driven Two-Pass Top-Down Routing • Experimental Results • Conclusion

  35. Experimental Setting • C++ language with LEDA library on a 1.2 GHz Sun Blade-2000 with 8GB memory • Compared our two-pass, top-down routing system (TTR) with MROR [Li et al., TCAD’07] • Λ-shaped multilevel router considering balanced density • Compared the density-CAA guided global routing of TTR with CMP-aware minimum pin-density global routing [Cho et al., ICCAD’06] • Minimum pin-density global routing + TTR detailed routing

  36. Routing Benchmarks • Academic: eleven MCNC benchmarks • Industrial: five Faraday benchmarks Faraday benchmarks MCNC benchmarks

  37. Comparison Metric • Comparison is based on the same metric used in the work of MROR [TCAD’07] • #Netmax: maximum # of nets crossing a tile • #Netavg_h: average # of nets horizontally crossing a tile • #Netavg_v: average # of nets vertically crossing a tile • σh: standard deviation of # of nets horizontally crossing a tile • σv: standard deviation of # of nets vertically crossing a tile • Reflects the wire density distribution for a routing result

  38. Experimental Results (MCNC) • All three routers achieved 100% routability • TTR reduced • #Netmax by 43% than TCAD’07 and 11% than ICCAD’06 • #Netavg_v by 34% than TCAD’07 and 5% than ICCAD’06 • #Netavg_h by 36% than TCAD’07 and 11% than ICCAD’06

  39. 30 30 30 25 25 25 20 20 20 15 15 15 10 10 10 5 5 5 0 0 0 Vertical Wire Crossing of S13207 MROR [TCAD’07] GR [ICCAD’06] +TTR framework TTR (Ours)

  40. Experimental Results (Faraday) • MROR [TCAD’07] cannot run designs where pins are distributed between layers 1 and 3 • TTR reduced • #Netmax by 25% than ICCAD’06 • #Netavg_v by 2% than ICCAD’06 • #Netavg_h by 2% than ICCAD’06

  41. Horizontal Wire Crossing of RISC1 GR [ICCAD’06] +TTR detailed routing TTR (Ours)

  42. Outline • CMP Introduction • Previous Work • Wire-Density Driven Two-Pass Top-Down Routing • Experimental Results • Conclusion

  43. Conclusion • Proposed a new full-chip density-driven routing system for CMP variation control • Voronoi-diagram based density CAA prerouting • Planarization-aware top-down global routing • Density-driven layer assignment + Delaunay-triangulation based track assignment • Top-down detailed routing • Reduced 43% and 11% maximum wire crossing on density tiles and achieved more balanced wire distribution than state-of-the-art previous works

  44. Q & A Thanks for your attention!

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