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Agenda

Agenda. 分析背景與目的 專利文件選擇 關鍵字分類 專利文件分群 專利品質分析 結論. 分析背景. High speed Low dissipation Low costs High profits. In Digital application, the transistor play the role of switch in the system just like a mechanical switch, it means that the key component to storage the 0 and 1.

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Agenda

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  1. Agenda • 分析背景與目的 • 專利文件選擇 • 關鍵字分類 • 專利文件分群 • 專利品質分析 • 結論

  2. 分析背景 High speed Low dissipation Low costs High profits In Digital application, the transistor play the role of switch in the system just like a mechanical switch, it means that the key component to storage the 0 and 1. Dimension increase in MOS (Advanced Process)  Device Performance Problems Logic Circuit Memory Circuit Hideo Sunami (2010)

  3. 分析目的 Process Migration Low? High? Model is verified by hardware data 是否可由Process Migration區分Patent Quality 的好壞？ 是否可從Patent Quality解釋期中報告的結論？

  4. 專利文件選擇

  5. 專利文件選擇 Patents: 835  23 H01L21/84 基板為半導體以外者，例如絕緣體者 H01L21/02 半導體裝置或其部件之製造或處理 H01L21/336 具有絕緣閘者 H01L21/8238 互補型場效應電晶體 H01L29/76 單極裝置

  6. 關鍵字處理 (NTFIDF) KP: 561  156  combining and deleting     80 (ave NTFIDF: 74.28)

  7. 關鍵字處理 (Deleting KP) Deleted 32 KPs

  8. 關鍵字處理 (Combining KP) Combined 295 KPs

  9. 關鍵字分類 (IC Design to Mask Fabrication) FEOL/BEOL Layout Mask Process flow (oxidation + PECVD + APCVD + sputtering + etching + implantation + diffusion + lithography + etc.) Process (oxidation/PECVD/APCVD/sputtering/etching/implantation/diffusion/lithography/etc.)

  10. 關鍵字分類 (IC Design and Devices) Device Component (substrate /source /drain /gate/well /etc.) Mask IC Device (substrate + source + drain + gate + well + etc.) FEOL/BEOL Layout

  11. 80 KPs  9 items 關鍵字分類

  12. 專利文件分群 using k-means clustering

  13. 專利品質分析 using PCA Medium Quality Low Quality High Quality Medium Quality

  14. 專利品質分析 High Low High Medium

  15. 專利品質分析

  16. 結論 是否可由Process Migration區分Patent Quality 的好壞？ 是否可從Patent Quality解釋期中報告的結論？

  17. Reference Bill McClean (2013), Samsung Jumps to #3 in 2012 foundry Ranking, Has Sights Set on #2 Spot in 2013, IC Insights, USA. Hideo Sunami (2010), Advances in Solid State Circuit Technologies, InTech, USA (first edition). Hossain M. Fahad, Muhammad M. Hussain (2012), Are Nanotube Architectures More Advantageous Than Nanowire Architectures For Field Effect Transistors?, Scientific Reports 2, ISSN (online): 2045-2322, USA. Mark Zwolinski, Electrical Variability due to Layout Dependent Effects: Analysis, Quantification, and Mitigation on 40 and 28nm SOC Designs, School of Electronics and Computer Science, university of Southampton, UK. Satoru Okubo (2005), CMOS Technology Evolves to High-Speed, Low-Dissipation, Nikkei Electronics Asia, Japan. 林鴻志 (2005), 奈米金氧半電晶體元件技術發展驅勢(I), NDL奈米通訊12卷3期, 台灣. 林鴻志 (2005), 奈米金氧半電晶體元件技術發展驅勢(II), NDL奈米通訊12卷3期, 台灣. 林鴻志 (2005), 奈米金氧半電晶體元件技術發展驅勢(III), NDL奈米通訊12卷3期, 台灣. 莊達人 (1995), VLSI製造技術, 高立圖書, 台灣 (第三版). 張瑞芬, 張力元, 吳俊逸, 樊晉源 (2013), 專利分析與智慧財產管理, 華泰文化, 台灣 (第一版). 菊地正典, 影山隆雄 (2010), 圖解電子裝置, 世茂出版社, 台灣 (第一版). 麥利 (2013), IEDM：英特爾與競爭對手決戰先進製程技術, EET電子工程專輯2013年2月號, 台灣.

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