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CLK. CPU Wrapper. RST. Pipelined CPU. Alignment Unit. Controller. Controller. Bus Sharing logic. I-Cache memory. D-Cache Memory . WISHBONE SYSTEM BUS. Word Alignment. The next problem we must solve MemAddr_OutReg is word aligned Address bits 1 and 0 are not used
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CLK CPU Wrapper RST Pipelined CPU Alignment Unit Controller Controller Bus Sharing logic I-Cache memory D-Cache Memory\ WISHBONE SYSTEM BUS
Word Alignment • The next problem we must solve • MemAddr_OutReg is word aligned • Address bits 1 and 0 are not used • Must do something about LH and LB which do not address the low-order portion of the word Because the processor sign/zero-extends the low-order portion of the word on a LH, LHU, LB, LBU, we just need to right-shift the contents depending on the offset! Note: this has implications for stores!
Word Alignment Memory [0x00004004] = 0x87654321 Byte 3 Byte 2 Byte 1 Byte 0 8 7 6 5 4 3 2 1 MemoryAddress(1:0) “11” “10” “01” “00” Halfword 1 Halfword 0 8 7 6 5 4 3 2 1 MemoryAddress(1:0) “10” “00”
Word Alignment Memory [0x00004004] = 0x87654321 0 0 0 0 0 0 2 1 Data in for LBU with MemoryAddress(1:0) = “00” 0 0 0 0 0 0 4 3 Data in for LBU with MemoryAddress(1:0) = “01” 0 0 0 0 0 0 6 5 Data in for LBU with MemoryAddress(1:0) = “10” 0 0 0 0 0 0 8 7 Data in for LBU with MemoryAddress(1:0) = “11” 0 0 0 0 4 3 2 1 Data in for LHU with MemoryAddress(1:0) = “00” 0 0 0 0 8 7 6 5 Data in for LHU with MemoryAddress(1:0) = “10”
MSB 32-bit Word from memory 32-bit Word To CPU LSB Alignment Unit • Three modes for the alignment unit • Word mode – pass all data, unshifted • Halfword mode – shift top two byte lanes to low two byte lane (if offset = 10) • Byte mode – shift high byte lanes to low order (dep. on offset) Address(0) Address(1) CPU will Sign extend if necessary
