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Chapter 12 CPU Structure and Function. HW: 12.4a, 12.7, 12.10. CPU Sequence. Fetch instructions Interpret instructions Fetch data Process data Write data. CPU With Systems Bus. CPU Internal Structure. Registers. CPU must have some working space (temporary or scratch pad storage)

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Chapter 12 CPU Structure and Function

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Chapter 12 cpu structure and function l.jpg

Chapter 12CPU Structure and Function

HW: 12.4a, 12.7, 12.10


Cpu sequence l.jpg

CPU Sequence

  • Fetch instructions

  • Interpret instructions

  • Fetch data

  • Process data

  • Write data


Cpu with systems bus l.jpg

CPU With Systems Bus


Cpu internal structure l.jpg

CPU Internal Structure


Registers l.jpg

Registers

  • CPU must have some working space (temporary or scratch pad storage)

  • Top level of memory hierarchy

  • Number and function vary between processor designs


User visible registers l.jpg

User Visible Registers

  • General Purpose

  • Data

  • Address

  • Control (Condition Codes)


General purpose registers l.jpg

General Purpose Registers

  • May be true general purpose

    May be used for data or addressing

  • May be restricted

  • Data

    • May include Accumulator

  • Addressing

    • May include Segment Register(s)


General purpose registers design decision l.jpg

General Purpose Registers Design Decision

  • Make them general purpose ?

    • Increase flexibility and programmer options

    • Increase instruction size & complexity

  • Make them specialized

    • Smaller (faster) instructions

    • Less flexibility


How many gp registers l.jpg

How Many GP Registers?

  • Between 8 – 32 ?

  • Fewer = more memory references

  • More does not reduce memory references and takes up processor real estate


How big l.jpg

How big?

  • Large enough to hold full address

  • Large enough to hold full word

    - Sometimes possible to combine two data registers


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Control & Status Registers

  • Program Counter

  • Instruction Decoding Register

  • Memory Address Register

  • Memory Buffer Register

  • Program Status Word


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Control - Condition Code Registers

  • CC: Sets of individual bits

    • e.g. result of last operation was zero

  • Can be read (implicitly) by programs

    • e.g. Jump if zero

  • Usually can not be set by programs


Program status word l.jpg

Program Status Word

  • A set of bits

  • Includes Condition Codes

  • Interrupt enable/disable

  • Supervisor State information

    - Kernel Mode - Not available to user programs

    (Used by operating system)

    (Allows privileged instructions to execute)


Other registers l.jpg

Other Registers

  • May have registers pointing to:

    • Process control blocks

    • Interrupt Vectors

  • Note: CPU design and operating system design are closely linked


Example register organizations l.jpg

Example Register Organizations


Instruction cycle with indirect l.jpg

Instruction Cycle with Indirect

Note: ‘Indirect’ allows for fetching data with indirect addressing


Data flow fetch diagram l.jpg

Data Flow (Fetch Diagram)


Data flow indirect diagram l.jpg

Data Flow (Indirect Diagram)


Instruction cycle state diagram l.jpg

Instruction Cycle State Diagram


Data flow instruction fetch l.jpg

Data Flow (Instruction Fetch)

  • Fetch

    • PC contains address of next instruction

    • Address moved to MAR

    • Address placed on address bus

    • Control unit requests memory read

    • Result placed on data bus, copied to MBR, then to IR

    • Meanwhile PC incremented by 1 (or more)


Data flow data fetch l.jpg

Data Flow (Data Fetch)

  • IR is examined

  • If indirect addressing, indirect cycle is performed

    • N bits of MBR transferred to MAR

    • Control unit requests memory read

    • Result (address of operand) moved to MBR


Data flow execute l.jpg

Data Flow (Execute)

  • May take many forms

  • Depends on instruction being executed

  • May include

    • Memory read/write

    • Input/Output

    • Register transfers

    • ALU operations


Data flow data store l.jpg

Data Flow (Data Store)

  • If indirect addressing, indirect cycle is performed

    • N bits of MBR transferred to MAR

    • Control unit requests memory read

    • Result (address of operand) moved to MBR


Data flow interrupt l.jpg

Data Flow (Interrupt)

  • Context Stored / Interrupt Acknowledged

  • Vector Fetched & Intr Serv Routine Addr => PC

  • Intr Serv Routine (Handler) executed

  • ….

  • Context Restored

  • Continue execution of main program


Prefetch l.jpg

Prefetch

Consider the instruction sequence as:

  • Fetch instruction

  • Execution instruction (often does not access main memory)

    Can fetch next instruction during execution of current instruction

  • Called instruction Prefetch


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Improved Performance with Prefetch

  • But not doubled:

    • Fetch usually shorter than execution

    • Any jump or branch means that prefetched instructions are not the required instructions

  • Maybe Prefetch more than one instruction ?

  • Maybe add more stages to improve performance ?


Pipelining l.jpg

Pipelining

Consider the instruction sequence as:

  • instruction fetch,

  • decode instruction,

  • fetch data,

  • execute instruction,

  • store result,

  • check for interrupt

    Consider it as an “assembly line” of operations.

    Then we can begin the next instruction assembly line sequence

    before the last has finished. Actually we can fetch the next

    instruction while the present one is being decoded.

    This is pipelining.


Two stage instruction pipeline l.jpg

Two Stage Instruction Pipeline


Define pipeline stations l.jpg

Define Pipeline “stations”

  • Fetch instruction (FI)

  • Decode Instruction (DI)

  • Calculate operands (CO)

  • Fetch Operands (FO)

  • Execute Instruction (EI)

  • Write Operand (WO)


Timing diagram for instruction pipeline operation l.jpg

Timing Diagram for Instruction Pipeline Operation


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The Effect of a Conditional Branch on Instruction Pipeline Operation

Instruction 3 is a conditional branch to instruction 15:


Alternative pipeline depiction l.jpg

Alternative Pipeline Depiction

Instruction 3 is conditional branch to instruction 15:


Speedup factors with instruction pipelining l.jpg

Speedup Factors with Instruction Pipelining


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Dealing with Branches – Possible approaches

  • Multiple Streams

  • Prefetch Branch Target

  • Loop buffer

  • Branch prediction

  • Delayed branching


Multiple streams l.jpg

Multiple Streams

  • Have two pipelines

  • Prefetch each branch into a separate pipeline

  • Use appropriate pipeline

    Challenges:

  • Leads to bus & register contention

  • Multiple branches lead to further pipelines being needed


Prefetch branch target l.jpg

Prefetch Branch Target

  • Target of branch is prefetched in addition to instructions following branch

  • Keep target until branch is executed

  • Used by IBM 360/91


Loop buffer l.jpg

Loop Buffer

  • Use Very fast memory (“Loop Buffer Cache”)

  • Maintained by fetch stage of pipeline

  • Check buffer before fetching from memory

  • Very good for small loops or jumps

  • Used by CRAY-1


Branch prediction l.jpg

Branch Prediction

  • Predict branch never taken

  • Predict branch always taken

  • Predict by opcode

  • Predict branch taken/not taken switch

  • Maintain branch history table


Predict branch taken not taken l.jpg

Predict Branch Taken / Not taken

  • Predict never taken

    • Assume that jump will not happen

    • Always fetch next instruction

    • 68020 & VAX 11/780, VAX will not prefetch after branch if a page fault would result (O/S v CPU design)

  • Predict always taken

    • Assume that jump will happen

    • Always fetch target instruction

Which is better?


Branch prediction by opcode switch l.jpg

Branch Prediction by Opcode / Switch

  • Predict by Opcode

    • Some instructions are more likely to result in a jump than thers

    • Can get up to 75% success

  • Taken/Not taken switch

    • Based on previous history

    • Good for loops


Maintain branch table l.jpg

Maintain Branch Table

  • Perhaps a cache table of three entries:

    - Address of branch

    - History of branching

    - Targets of branch


Intel 80486 pipelining l.jpg

Intel 80486 Pipelining

  • Fetch (Fetch)

    • From cache or external memory

    • Put in one of two 16-byte prefetch buffers

    • Fill buffer with new data as soon as old data consumed

    • Average 5 instructions fetched per load

    • Independent of other stages to keep buffers full

  • Decode stage 1 (D1)

    • Opcode & address-mode info

    • At most first 3 bytes of instruction

    • Can direct D2 stage to get rest of instruction

  • Decode stage 2 (D2)

    • Expand opcode into control signals

    • Computation of complex address modes

  • Execute (EX)

    • ALU operations, cache access, register update

  • Writeback (WB)

    • Update registers & flags

    • Results sent to cache & bus interface write buffers


80486 instruction pipeline examples l.jpg

80486 Instruction Pipeline Examples


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