Perkenalan sequensial
This presentation is the property of its rightful owner.
Sponsored Links
1 / 26

Perkenalan Sequensial PowerPoint PPT Presentation


  • 46 Views
  • Uploaded on
  • Presentation posted in: General

Perkenalan Sequensial. Gambaran:. Model Rangkaian Sequensial. x 1. Logika Kombinasional. z 1. z m. x n. Y 1. Y r. y 1. y r. Memori. Memori. 0. 1. 1. 1. Q. B. 1. 0. 1. 0. A=0. Latch. Q. 0. 1. 0. R=0. S=1. Q. 1. 0. 0. 1. R=1. S=0. SR Latch. (Set). Symbol:.

Download Presentation

Perkenalan Sequensial

An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -

Presentation Transcript


Perkenalan sequensial

Perkenalan Sequensial


Gambaran

Gambaran:


Model rangkaian sequensial

Model Rangkaian Sequensial

x1

LogikaKombinasional

z1

zm

xn

Y1

Yr

y1

yr

Memori


Memori

Memori

0

1

1

1

Q

B

1

0

1

0

A=0


Latch

Latch

Q

0

1

0

R=0

S=1

Q

1

0

0

1

R=1

S=0


Sr latch

SR Latch

(Set)

Symbol:

(Reset)


Tabel kebenaran sr latch

Tabel Kebenaran SR-Latch

S(t) R(t) Q(t) Q’ = Q( t+ )

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 0

1 0 0 1

1 0 1 1

1 1 0 x

1 1 1 x

Hold

Reset

Set

Forbidden


Timing diagram

Timing Diagram

S

R

Q

S

R

Q


Sr latch dengan gerbang gated sr latch

R

Q

S

Q

SR Latch dengan Gerbang(Gated SR Latch)

R

Symbol:

Clock

or

enb

S

CLK


Timing diagram1

Timing Diagram

CK

S

R

Q

CK

S

R

Q


Delay latch

Delay Latch

X

S

D

Q

Symbol:

D

Q

C

CLK

Q’

R

Y


Tabel kebenaran d latch

Tabel Kebenaran D-Latch

X Y C Q(t) Q’= Q( t+ )

0 0 1 Q0 Q0’ Store

0 1 1 0 1 Reset

1 0 1 1 0 Set

1 1 1 1 1 Disallowed

X X 0 Q0 Q0’ Store

D(t) C Q(t) Q+ = Q( t+ )

0 1 0 0

0 1 1 0

1 1 0 1

1 1 1 1

x 0 Q(t) Q+ = Q( t+ )


Timing diagram2

Timing Diagram

CK

D

Q

CK

D

Q


Jk latch

J

Q

K

Q

JK Latch

J

Symbol:

Clock

K

CLK


Perkenalan sequensial

Tabel Kebenaran JK-Latch

J K C Q(t) Q( t+ )

  • 0 0 1 Q0 Q0

  • 0 1 1 0 0

  • 0 1 1 1 0

  • 1 0 1 0 1

  • 0 1 1 1

  • 1 1 1 0 1 Togle

  • 1 1 1 1 0 Togle

  • X X 0 Q0 Q0


Timing diagram3

Timing Diagram


Master slave sr flip flop

Master-slave SR flip-flop


Prinsip kerja

Prinsip Kerja


Prinsip kerja1

Prinsip Kerja


Master slave d flip flop

Master-slave D flip-flop


Prinsip kerja2

Prinsip Kerja


Master slave jk flip flop

Master-slave JK flip-flop

Q

1

R

R-S

Latch

J

R

1

R-S

Latch

1

1

P

0

Qm

0

Qs

K

0

S

Q

S

0

Clock


Edge triggered d flip flop

Edge triggered D flip-flop


Edge triggered jk flip flop

Edge triggered JK flip-flop


Edge triggered t flip flop

Edge triggered T flip-flop


Flip flop dan latch

R

R

Q

Q

S

S

Flip-Flop dan Latch

Clock:

R

Q

S

CLK


  • Login