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Single Event and Total Dose Effects on SEU (Single Event Upset)-Hardened Antifuse FPGA

Single Event and Total Dose Effects on SEU (Single Event Upset)-Hardened Antifuse FPGA. J.J. Wang 1 , R. Katz 2 , I. Kleyner 3 , B. Cronquist 1 , J. McCollum 1 , W. Parker 1 , D. Yu 1 , and R. Chan 1 1 Actel Corporation, Sunnyvale, CA94086

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Single Event and Total Dose Effects on SEU (Single Event Upset)-Hardened Antifuse FPGA

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  1. Single Event and Total Dose Effects on SEU (Single Event Upset)-Hardened Antifuse FPGA J.J. Wang1, R. Katz2, I. Kleyner3, B. Cronquist1, J. McCollum1, W. Parker1, D. Yu1, and R. Chan1 1Actel Corporation, Sunnyvale, CA94086 2NASA Goddard Space Flight Center, Greenbelt, MD20771 3Orbital Sciences Corporation, Greenbelt, MD20771 Wang 1 C4

  2. Outline • Device and Technology • Single Event Effects Test and Results • Total Ionizing Dose Test and Results • Summary Wang 2 C4

  3. RT54SX32S/72S • Manufactured by 0.25 µm technology at MEC (Matsushita Electronic Industrial Co., Ltd.) foundry. • Very low power (68 mW standby). • Configurable I/O, for 3.3/5.0V PCI, LVTTL, TTL and CMOS levels. • 5.0V Input tolerance and output drive. • Hot swapping. • JTAG, IEEE standard 1149.1. Wang 3 C4

  4. RT54SX32S/72S Wang 4 C4

  5. D A A B C B A Q B C A C B G C SEU-Hardened Register Cell • Conceptual triple redundant latch as shown in above is implemented in the master and slave latch respectively. • The SEU-hardened register is checked at the circuit level to be hazard free. Wang 5 C4

  6. SEE (Single Event Effect) Testing • DUT is programmed as Shift Registers, total 800 flip-flops (register cells). • Checkerboard pattern running at 1 MHz. • BNL SEU facility, Ions: 279 MeV Br, 321 MeV I. Wang 6 C4

  7. SEE Testing Issues • Boundary scan (JTAG) shift registers are not hardened. • Early tests on RT54SX32S inadvertently left the TRSTB pin floating. • The upset in the JTAG TAP controller caused false errors detected at the output of a counter/register design. • JTAG upset detected by: • Abnormal ICC fluctuations (tens to hundreds of mA). • Comparing the output of a standard shift register and a TMR (at the user level) shift register on the the same die. Wang 7 C4

  8. SEE Testing Issues • Upset due to double hit at shallow angles cannot be tested (will be analyzed by simulation). • Using very high flux will create false upset due to double hit. • Multi-layer metal interconnects are thicker for newer device, causing penetration problems at high tilt angles (q in LETeff= LET/cosq). • RT54SX32S has 3 metal layers, a total of 6 µm dielectric/metal plus 7 µm polyimide top cap. • RT54SX72S has 4 metal layers, a total of 7.5 µm dielectric/metal plus 7 µm polyimide top cap. Wang 8 C4

  9. SEE Test Results - RT54SX32S Wang 9 C4

  10. SEE Test Results - RT54SX72S Wang 10 C4

  11. SEE Test Results - RT54SX32S • SEU • Single digit error per run (total fluence=107 ions/cm2) sometimes for LET > 60 MeV-cm2/mg. • SEL (Single Event Latchup) • Immune up to 104 MeV-cm2/mg (VCCI/VCCA=5.5/2.75V). • SEDR (Single Event Dielectric-Antifuse Rupture) • Immune up to Iodine (60 MeV-cm2/mg) at normal incidence (which is the worst case), VCCA=3.0V. Wang 11 C4

  12. SEE Test Results - RT54SX72S • SEU • One error per run (total fluence=107 ions/cm2) sometimes for LET > 50 MeV-cm2/mg. • SEL • Immune up to 110 MeV-cm2/mg (VCCI/VCCA=5.5/2.75V). • SEDR • For Iodine (60 MeV-cm2/mg) at normal incidence (which is the worst case), none at VCCA=2.75V, 1 or 2 antifuse rupture at VCCA=2.85V. • 1 rupture generates ~10mA permanent ICC increase. • DUT were functional after multiple ruptures. • Using CRÈME96 model (100 mil Al shielding, Solar minimum), rupture rate < 3.94x10-9 ruptures/device/year (1 rupture per device per 250 million years). Wang 12 C4

  13. SEE Test Results - SEDR RH1020_ONO_5V RTSX16_MM_3.3V ASX16_MM_3.3V RTSX32S_MM_2.5V SX16_MM_3.3V RTSX72S_MM_2.5V Wang 13 C4

  14. SEU Modes for Triple Redundant Latch Heavy Ion Strike Sensitive Vol Sensitive Vol Sub-latch 1 Sub-latch 3 Field between two actives Sensitive volume in sub-latch 1 Sensitive volume in sub-latch 3 Ion Strike Mode 1 Single Ion Double Strike Mode 2 Indirect Ion Strike Wang 14 C4

  15. SEU Mode 1 SPICE Simulations - Single Ion Double Strike D A A Heavy Ion Strike B Sensitive Vol Sensitive Vol C Sub-latch 1 Sub-latch 3 B A Q B Ion Strike C A C B G C Ion Strike Wang 15 C4

  16. SEU Mode 1 SPICE Simulations - Single Ion Double Strike Voltage (volt) Latch 2 2 1 Latch 1 & 3 Ion Strike 0 2 1 0 Time (nsec) Wang 16 C4

  17. SEU Mode 1 SPICE Simulations - Single Ion Double Strike • Heavy Ion test facility cannot test this mode because the very shallow incidence angle (<1.5 degree off die surface). • The critical charge is simulated as 0.15 pC, and the collection depth of the same technology is extracted from previous experiment as 1µm, the threshold LET is 13.6 MeV-cm2/mg. • Using SPACERAD 4.0, SEU rate for GEO orbit, 100 mil Al shielding and Solar min, is calculated 1.36 x10-11 upset/bit-day Wang 17 C4

  18. SEU Mode 2 Mixed-Mode Simulations - Indirect Ion Strike D A A B C B A Q B C A C B G C Field between two actives Sensitive junction in sub-latch 3 Sensitive junction in sub-latch 1 Ion Strike Wang 18 C4

  19. SEU Mode 2 Mixed-Mode Simulations - Indirect Ion Strike Voltage (volt) Latch 2 Latch 1 & 3 Wang 19 C4

  20. SEU Mode 2 Mixed-Mode Simulations - Indirect Ion Strike Voltage (volt) Latch 2 Latch 1 & 3 Wang 20 C4

  21. SEU Mode 2 Mixed-Mode Simulations - Indirect Ion Strike • The threshold LET of the hardened register is determined as 120 MeV-cm2/mg. The upset measured by beam test is SET induced • User level TMR hardened shift register has similar rate as non-TMR shift register. • Upset rate is dependent on data frequency, static mode has no upset (observed by ESA/SAAB). • The upset rate of register in mode 2 is much lower than Mode 1 “single ion double”. Wang 21 C4

  22. Total Ionizing Dose Testing • Radiation source: Co60 (NASA/GSFC, DMEA) • Dose rate: 0.42 rad(Si)/hr, 0.5 krad(Si)/hr, 1 krad(Si)/hr, 60 krad(Si)/hr • Biased at VCCI/VCCA = 3.3V/2.5V • Static data mode • Room Temperature • In-situ functionality, ICC monitoring • In-situ tPD measurement Wang 22 C4

  23. Total Ionizing Dose -RT54SX32S Propagation Delay • Propagation delay is significantly degraded by total dose effects, previous technologies (ONO or MIM) have negligible degradation before losing functionality. • The common sense “lower VCC improves total dose tolerance” doesn’t apply in this case. • Reason: Charge pump degrades by radiation induced leakage current loading. • Before dosage reach final functional tolerance, 0.25 µm degrades significantly while 0.6 µm doesn’t. • SPICE simulation confirmed > 20% delay when Vpump dropped to 2.5V (normal 5.0V). Wang 23 C4

  24. Isolation Device Signal Charge Pump Logic Module Input Buffer Total Ionizing Dose - RT54SX32S Charge Pump • A global charge pump circuit controls the isolation devices for programming the antifuse. • VPUMP~5V (for 0.25µm) to turn on isolation device (NMOS pass transistor) during operation. • During programming isolation device is turned off. Wang 24 C4

  25. Total Ionizing Dose - RT54SX32SCharge Pump Wang 25 C4

  26. Total Ionizing Dose - RT54SX32SPropagation Delay Wang 26 C4

  27. Total Ionizing Dose - RT54SX32SPropagation Delay • Propagation delay degradation is dependent on the dose rate. Wang 27 C4

  28. Conclusion/Future Work • SEU hardened register (flip-flop) module proven by beam test as designed. • RTSXS family has very high tolerance of SEE • SEL immune. • SEU not measurable in hardened register, small effect of SET detected (1MHz data rate). • SEDR effect is negligible in any conceivable mission. • Propagation delay degradation due to charge pump degradation limits total dose tolerance, this effect is dose rate dependent. • Charge pump is modified in RT54SX72S to improve the total dose tolerance. Wang 28 C4

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