Cmput329 fall 2003
This presentation is the property of its rightful owner.
Sponsored Links
1 / 10

CMPUT329 - Fall 2003 PowerPoint PPT Presentation


  • 145 Views
  • Uploaded on
  • Presentation posted in: General

CMPUT329 - Fall 2003. TopicE: Clock Skew and Clock Gating José Nelson Amaral. Timing With Propagation Delays. Clock Skew. Clock signal may not reach all flip-flops simultaneously.

Download Presentation

CMPUT329 - Fall 2003

An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -

Presentation Transcript


Cmput329 fall 2003

CMPUT329 - Fall 2003

TopicE: Clock Skew and Clock Gating

José Nelson Amaral

CMPUT 329 - Computer Organization and Architecture II


Timing with propagation delays

Timing With Propagation Delays

CMPUT 329 - Computer Organization and Architecture II


Clock skew

Clock Skew

  • Clock signal may not reach all flip-flops simultaneously.

  • Output changes of flip-flops receiving “early” clock may reach D inputs of flip-flops with “late” clock too soon.

CMPUT 329 - Computer Organization and Architecture II


Clock skew1

Clock Skew

Reasons for slowness:(a) wiring delays

(b) capacitance

(c) incorrect design

CMPUT 329 - Computer Organization and Architecture II


Clock skew calculation

Clock-skew calculation

  • tffpd(min) + tcomb(min)-thold-tskew(max) > 0

  • First two terms are minimum time after clock edge for a D input to change

  • Hold time is earliest time that the input may change

  • Clock skew subtracts from the available hold-time margin

  • Compensating for clock skew:

    • Longer flip-flop propagation delay

    • Explicit combinational delays

    • Shorter (even negative) flip-flop hold times

CMPUT 329 - Computer Organization and Architecture II


Example of bad clock distribution

Example of bad clock distribution

CMPUT 329 - Computer Organization and Architecture II


Clock distribution in asics

Clock distribution in ASICs

  • This is what a typical ASIC router will do if you don’t lay out the clock by hand.

CMPUT 329 - Computer Organization and Architecture II


Clock tree solution

“Clock-tree” solution

  • Often laid out by hand

  • Wide,fast metal (low R ==> fast RC time constant)

CMPUT 329 - Computer Organization and Architecture II


Gating the clock

Gating the clock

  • Definitely a no-no

    • Glitches possible if control signal (CLKEN) is generated by the same clock

    • Excessive clock skew in any case.

CMPUT 329 - Computer Organization and Architecture II


If you really must gate the clock

If you really must gate the clock...

CMPUT 329 - Computer Organization and Architecture II


  • Login