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Lecture 22: Multistage Amps. Prof. Niknejad. Lecture Outline. Finish Current Mirrors An Example Using Cascodes Multistage Amps Cascode Amplifier: Magic!. The Integrated “Current Mirror”. M 1 and M 2 have the same V GS If we neglect CLM ( λ =0), then the drain currents are equal

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Lecture 22: Multistage Amps

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Lecture 22 multistage amps l.jpg

Lecture 22:Multistage Amps

Prof. Niknejad


Lecture outline l.jpg

Lecture Outline

  • Finish Current Mirrors

  • An Example Using Cascodes

  • Multistage Amps

  • Cascode Amplifier: Magic!

University of California, Berkeley


The integrated current mirror l.jpg

The Integrated “Current Mirror”

  • M1 and M2 have the same VGS

  • If we neglect CLM (λ=0), then the drain currents are equal

  • Since λ is small, the currents will nearly mirror one another even if Vout is not equal to VGS1

  • We say that the current IREF is mirrored into iOUT

  • Notice that the mirror works for small and large signals!

High Res

Low Resis

University of California, Berkeley


Current mirror as current source l.jpg

Current Mirror as Current Source

  • The output current of M2 is only weakly dependent on vOUT due to high output resistance of FET

  • M2 acts like a current source to the rest of the circuit

University of California, Berkeley


Small signal resistance of i source l.jpg

Small-Signal Resistance of I-Source

University of California, Berkeley


Improved current sources l.jpg

Improved Current Sources

Goal: increase roc

Approach: look at amplifier output resistance results … to see topologies that boost resistance

Looks like the output impedance of a common-source amplifier with source degeneration

University of California, Berkeley


Effect of source degeneration l.jpg

Effect of Source Degeneration

  • Equivalent resistance loading gate is dominated by the diode resistance … assume this is a small impedance

  • Output impedance is boosted by factor

University of California, Berkeley


Cascode or stacked current source l.jpg

Cascode (or Stacked) Current Source

Insight: VGS2 = constant AND

VDS2 = constant

Small-Signal Resistance roc:

University of California, Berkeley


Drawback of cascode i source l.jpg

Drawback of Cascode I-Source

Minimum output voltage to keep both transistors in saturation:

University of California, Berkeley


Current sinks and sources l.jpg

Current Sinks and Sources

Sink: output current goes to ground

Source: output current comes from voltage supply

University of California, Berkeley


Current mirrors l.jpg

Current Mirrors

Idea: we only need one reference current to set up all the currentsources and sinks needed for a multistage amplifier.

University of California, Berkeley


Multistage amplifiers l.jpg

Multistage Amplifiers

  • Necessary to meet typical specifications for any of the 4 types

  • We have 2 flavors (NMOS, PMOS) of CS, CG, and CD and the npn versions of CE, CB, and CC (for a BiCMOS process)

  • What are the constraints?

    • Input/output resistance matching

    • DC coupling (no passive elements to block the signal)

University of California, Berkeley


Summary of cascaded amplifiers l.jpg

Summary of Cascaded Amplifiers

  • General goals:

  • Boost the gain parameter (except for buffers)

  • Optimize the input and output resistances

University of California, Berkeley


Start two stage voltage amplifier l.jpg

CE2

CE1

Start: Two-Stage Voltage Amplifier

  • Use two-port models to explore whether the combination “works”

CE1,2

Results of new 2-port: Rin= Rin1,Rout= Rout2

University of California, Berkeley


Add a third stage cc l.jpg

Add a Third Stage: CC

Goal: reduce the output resistance (important spec. for a voltage amp)

CE2

CC3

CE1

Output resistance:

University of California, Berkeley


Using cmos stages l.jpg

Using CMOS Stages

CS2

CD3

CS1

Input resistance:

Voltage gain (2-port parameter):

Output resistance:

University of California, Berkeley


Multistage current buffers l.jpg

Multistage Current Buffers

Are two cascaded common-base stages better than one?

Input resistance: Rin = Rin1

University of California, Berkeley


Two port models l.jpg

Two-Port Models

Output impedance of stage #1 (large)

University of California, Berkeley


Common gate 2 nd stage l.jpg

Common-Gate 2nd Stage

University of California, Berkeley


Second design issue dc coupling l.jpg

Second Design Issue: DC Coupling

Constraint: large inductors and capacitors are not available

Output of one stage is directly connected to the input of the next stage  must consider DC levels … why?

3.2V

University of California, Berkeley


Alternative cg cc cascade l.jpg

Alternative CG-CC Cascade

Use a PMOS CD Stage: DC level shifts upward

3.2V

University of California, Berkeley


Cg cascade dc biasing l.jpg

CG Cascade: DC Biasing

Two stages can have different supply currents

Extreme case:

IBIAS2 = 0 A

University of California, Berkeley


Cg cascade sharing a supply l.jpg

CG Cascade: Sharing a Supply

First stage has no currentsupply of its own  its outputresistance is modified

University of California, Berkeley


The cascode configuration l.jpg

The Cascode Configuration

Common source / common gatecascade is one version of a cascode

(all have shared supplies)

DC bias:

Two-port model: first stage has no current supply of its own

University of California, Berkeley


Cascode two port model l.jpg

Cascode Two-Port Model

Output resistance of first stage =

Why is the cascode such an important configuration?

University of California, Berkeley


Miller capacitance of input stage l.jpg

Miller Capacitance of Input Stage

Find the Miller capacitance for Cgd1

Input resistance to common-gatesecond stage is low  gain acrossCgd1 is small.

University of California, Berkeley


Two port model with capacitors l.jpg

Two-Port Model with Capacitors

Miller capacitance:

University of California, Berkeley


Generating multiple dc voltages l.jpg

Generating Multiple DC Voltages

Stack-up diode-connected MOSFETs or BJTs and run a reference current through them  pick off voltages from gates or bases as references

University of California, Berkeley


Multistage amplifier design examples l.jpg

Multistage Amplifier Design Examples

Start with basic two-stage transconductance amplifier:

Why do this combination?

University of California, Berkeley


Two stage amplifier topology l.jpg

Two-Stage Amplifier Topology

Direct DC connection: use NMOS then PMOS

University of California, Berkeley


Current supply design l.jpg

Current Supply Design

Assume that the reference is a “sink” set by a resistor

Must mirror the reference current and generate a sink for iSUP 2

University of California, Berkeley


Use basic current supplies l.jpg

Use Basic Current Supplies

University of California, Berkeley


Complete amplifier topology l.jpg

Complete Amplifier Topology

What’s missing? The device dimensions and the bias

voltage and reference resistor

University of California, Berkeley


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