Lecture 22: Multistage Amps

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# Lecture 22: Multistage Amps - PowerPoint PPT Presentation

Lecture 22: Multistage Amps. Prof. Niknejad. Lecture Outline. Finish Current Mirrors An Example Using Cascodes Multistage Amps Cascode Amplifier: Magic!. The Integrated “Current Mirror”. M 1 and M 2 have the same V GS If we neglect CLM ( λ =0), then the drain currents are equal

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### Lecture 22:Multistage Amps

Lecture Outline
• Finish Current Mirrors
• An Example Using Cascodes
• Multistage Amps
• Cascode Amplifier: Magic!

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The Integrated “Current Mirror”
• M1 and M2 have the same VGS
• If we neglect CLM (λ=0), then the drain currents are equal
• Since λ is small, the currents will nearly mirror one another even if Vout is not equal to VGS1
• We say that the current IREF is mirrored into iOUT
• Notice that the mirror works for small and large signals!

High Res

Low Resis

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Current Mirror as Current Source
• The output current of M2 is only weakly dependent on vOUT due to high output resistance of FET
• M2 acts like a current source to the rest of the circuit

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Small-Signal Resistance of I-Source

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Improved Current Sources

Goal: increase roc

Approach: look at amplifier output resistance results … to see topologies that boost resistance

Looks like the output impedance of a common-source amplifier with source degeneration

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Effect of Source Degeneration
• Equivalent resistance loading gate is dominated by the diode resistance … assume this is a small impedance
• Output impedance is boosted by factor

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Cascode (or Stacked) Current Source

Insight: VGS2 = constant AND

VDS2 = constant

Small-Signal Resistance roc:

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Drawback of Cascode I-Source

Minimum output voltage to keep both transistors in saturation:

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Current Sinks and Sources

Sink: output current goes to ground

Source: output current comes from voltage supply

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Current Mirrors

Idea: we only need one reference current to set up all the current sources and sinks needed for a multistage amplifier.

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Multistage Amplifiers
• Necessary to meet typical specifications for any of the 4 types
• We have 2 flavors (NMOS, PMOS) of CS, CG, and CD and the npn versions of CE, CB, and CC (for a BiCMOS process)
• What are the constraints?
• Input/output resistance matching
• DC coupling (no passive elements to block the signal)

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• General goals:
• Boost the gain parameter (except for buffers)
• Optimize the input and output resistances

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CE2

CE1

Start: Two-Stage Voltage Amplifier
• Use two-port models to explore whether the combination “works”

CE1,2

Results of new 2-port: Rin= Rin1,Rout= Rout2

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Goal: reduce the output resistance (important spec. for a voltage amp)

CE2

CC3

CE1

Output resistance:

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Using CMOS Stages

CS2

CD3

CS1

Input resistance:

Voltage gain (2-port parameter):

Output resistance:

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Multistage Current Buffers

Are two cascaded common-base stages better than one?

Input resistance: Rin = Rin1

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Two-Port Models

Output impedance of stage #1 (large)

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Common-Gate 2nd Stage

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Second Design Issue: DC Coupling

Constraint: large inductors and capacitors are not available

Output of one stage is directly connected to the input of the next stage  must consider DC levels … why?

3.2V

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Use a PMOS CD Stage: DC level shifts upward

3.2V

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Two stages can have different supply currents

Extreme case:

IBIAS2 = 0 A

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First stage has no currentsupply of its own  its outputresistance is modified

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The Cascode Configuration

Common source / common gatecascade is one version of a cascode

(all have shared supplies)

DC bias:

Two-port model: first stage has no current supply of its own

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Cascode Two-Port Model

Output resistance of first stage =

Why is the cascode such an important configuration?

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Miller Capacitance of Input Stage

Find the Miller capacitance for Cgd1

Input resistance to common-gatesecond stage is low  gain acrossCgd1 is small.

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Two-Port Model with Capacitors

Miller capacitance:

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Generating Multiple DC Voltages

Stack-up diode-connected MOSFETs or BJTs and run a reference current through them  pick off voltages from gates or bases as references

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Multistage Amplifier Design Examples

Why do this combination?

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Two-Stage Amplifier Topology

Direct DC connection: use NMOS then PMOS

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Current Supply Design

Assume that the reference is a “sink” set by a resistor

Must mirror the reference current and generate a sink for iSUP 2

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Use Basic Current Supplies

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Complete Amplifier Topology

What’s missing? The device dimensions and the bias

voltage and reference resistor

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