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TMS320DM642. High-Performance Digital Media Processor (TMS320DM642) – 500-, 600-MHz Clock Rate – Eight 32-Bit Instructions/Cycle – 4000, 4800 MIPS – Fully Software-Compatible With C64x. VelociTI.2 . Extensions to VelociTI . Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x . DSP Core

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TMS320DM642

High-Performance Digital Media Processor (TMS320DM642)

– 500-, 600-MHz Clock Rate

– Eight 32-Bit Instructions/Cycle

– 4000, 4800 MIPS

– Fully Software-Compatible With C64x.

VelociTI.2. Extensions to VelociTI.

Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x. DSP Core

– Eight Highly Independent Functional Units With VelociTI.2. Extensions:

– Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad

8-Bit Arithmetic per Clock Cycle – Two Multipliers Support Four 16 x 16-Bit Multiplies

(32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies

(16-Bit Results) per Clock Cycle

– Load-Store Architecture WithNon-Aligned Support

– 64 32-Bit General-Purpose Registers

– Instruction Packing Reduces Code Size

– All Instructions Conditional


Instruction Set Features

– Byte-Addressable (8-/16-/32-/64-Bit Data)

– 8-Bit Overflow Protection

– Bit-Field Extract, Set, Clear

– Normalization, Saturation, Bit-Counting

– VelociTI.2. Increased Orthogonality

2级CACHE数量不同与 TMS320C6416

L1/L2 Memory Architecture

– 128K-Bit (16K-Byte) L1P Program Cache

(Direct Mapped)

– 128K-Bit (16K-Byte) L1D Data Cache

(2-Way Set-Associative)

– 2M-Bit (256K-Byte) L2 Unified Mapped

RAM/Cache (Flexible RAM/Cache Allocation)


C64X DSP 核心


外挂存储器

64-Bit External Memory Interface (EMIF)

– Glueless Interface to Asynchronous

Memories (SRAM and EPROM) and

Synchronous Memories (SDRAM,

SBSRAM, ZBT SRAM, and FIFO)

– 1024M-Byte Total Addressable External

Memory Space

极限空间比DAM6416小


10/100 Mb/s Ethernet MAC (EMAC)

– IEEE 802.3 Compliant

– Media Independent Interface (MII)

– 8 Independent Transmit (TX) and

8 Independent Receive (RX) Channels

直接以太网集成


Three Configurable Video Ports

– Providing a Glueless I/F to Common

Video Decoder and Encoder Devices

– Supports Multiple Resolutions and

Standards

– Supports RAW Video I/O

– Transport Stream Interface Mode

直接图象接口不同与TMS320C6416

VCXO Interpolated Control Port (VIC)

– Supports Audio/Video Synchronization

Host-Port Interface (HPI) [32-/16-Bit]

主机接口与MS320C6416相同,速度快

32-Bit/66-MHz, 3.3-V Peripheral Component

Interconnect (PCI) Master/Slave Interface

Conforms to PCI Specification 2.2



图象接口的细节

Three Configurable Video Ports

– Providing a Glueless I/F to Common

Video Decoder and Encoder Devices

– Supports Multiple Resolutions and

Standards

– Supports RAW Video I/O

– Transport Stream Interface Mode


Enhanced Direct-Memory-Access (EDMA)

Controller (64 Independent Channels)

Management Data Input/Output (MDIO)

Three 32-Bit General-Purpose Timers

Flexible PLL Clock Generator

Sixteen General-Purpose I/O (GPIO) Pins

Inter-Integrated Circuit (I2C) Bus

Multichannel Audio Serial Port (McASP)

– Eight Serial Data Pins

– Wide Variety of I2S and Similar Bit

Stream Format

– Integrated Digital Audio I/F Transmitter

Supports S/PDIF, IEC60958-1, AES-3,

CP-430 Formats

单独与

TMS320C6416

的多通道音频串口



多通道串口

Two Multichannel Buffered Serial Ports

IEEE-1149.1 (JTAG†)

Boundary-Scan-Compatible

548-Pin Ball Grid Array (BGA) Package (GDK Suffix), 0.8-mm Ball Pitch

548-Pin Ball Grid Array (BGA) Package (GNZ Suffix), 1.0-mm Ball Pitch

0.13-μm/6-Level Cu Metal Process (CMOS)

3.3-V I/Os, 1.2-V Internal (-500)

3.3-V I/Os, 1.4-V Internal (-600)


Improvement

VelociTITM C62xTM

VelociTI.2TM C64xTM

Overall Performance

TMS320DM642 (DM642) device is based on the second-generation high-performance, advanced VelociTI.

very-long-instruction-word (VLIW) architecture (VelociTI.2.) developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. 一代、二代的差别

4x

150-300

600-1100

MHz

4x

4800-8800

1200-2400

MIPS

8x

300-600

16-bit MMACs

2400-4400

16x

8-bit MMACs

4800-8800

300-600

8x

Special purposeinstructions

Communications

General

15x

Special purposeinstructions

Imaging

General

25%

Code size

reduction

Advanced instruction

packing

10X


语音压缩的必要性

图像压缩的必要性


  • xDSL modems

  • Pooled modems、3G基站

  • 无线以太网

  • 企业交换机 PBX,ATM

  • 多路语音识别

  • 多媒体网关

  • 网络摄像机

  • 安全认证

  • 二维或三维条形码识别

  • 高速打印机

  • 网络设备开发平台

  • 图像实时监控

  • 图像采集、压缩、视频输出

  • 高速实时数据采集与处理

  • 雷达信号处理

  • 软件无线电

  • 医疗设备

视频监控

顶置盒

Medical Imaging


The DM642 DSP possesses the perational flexibility of high-speed controllers and the numerical capability of array processors.

——适合的应用

The DM642 can produce four 32-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. The

——速度计算关系

The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache.

——第一级CACHE直接MAP

The Level 2 memory/cache (L2) consists of an 2-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

——第二级CACHE可以灵活配置


The peripheral set includes: three configurable video ports; a 10/100 Mb/s Ethernet MAC (EMAC); a management data input/output (MDIO) module; a VCXO interpolated control port (VIC); one multichannel buffered audio serial port (McASP0); an inter-integrated circuit (I2C) Bus module; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral component interconnect (PCI); a 16-pin general-purpose input/output port (GP0) with programmable interrupt/event generation modes; and a 64-bit glueless external memory interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and peripherals.

——多功能辅助外围设备


The DM642 device has three configurable video port peripherals (VP0, VP1, and VP2). These video port peripherals provide a glueless interface to common video decoder and encoder devices. All three Video Port peripherals have the capability to operate as a video-capture port, a video-display port, or a transport stream interface (TSI) capture port. The DM642 video port peripherals support multiple resolutions and video standards (e. g., CCIR601, ITU–BT.656, BT.1120, SMPTE 125M, 260M, 274M, and 296M).

——适合各个标准

These three video port peripherals are configurable and can support either video capture and/or video display modes. Each video port consists of two channels — A and B with a 5120-byte capture/display buffer that is splittable between the two channels.

——视频端口功能

For capture operation, the video port can operate as two 8/10-bit channels of BT.656 or two 8/10-bit channel of raw video capture; or as a single channel of 8/10-bit BT.656, 8/10-bit raw video, 16/20-bit Y/C video, 16/20-bit raw video, or 8-bit TSI.

——视频组合使用


For display operation, the video port can operate as a single channel (using only channel A) of 8/10-bit BT.656 display, 8/10-bit raw video display, 16/20-bit Y/C video display, or 16/20-bit raw video display. Also, in the display mode of operation, the video port is capable of operating in a two-channel 8/10-bit raw mode in which two channels are locked to the same timing. For more details on the Video Port peripherals, see the TMS320DM642 Technical Overview (literature number SPRU615) or the TMS320C64x Video Port/VXCO Interpolated Control (VIC) Port Reference Guide (literature number SPRU629).

——视频输出组合配置

  • BT.656-3 defines a schema for the digital interconnection of television video signals in conjunction

  • BT.1120-1 - Digital interfaces for 1125/60 and 1250/50 HDTV studio signals

  • SMPTE 125M (was RP 125) The SMPTE recommended practice for bit-parallel digital interface for component video signals. SMPTE 125M defines the parameters required to generate and distribute component video signals on a parallel interface.


CCIR601 single channel (using only channel A) of 8/10-bit BT.656 display, 8/10-bit raw video display, 16/20-bit Y/C video display, or 16/20-bit raw video display. Also, in the display mode of operation, the video port is capable of operating in a two-channel 8/10-bit raw mode in which two channels are locked to the same timing. For more details on the Video Port peripherals, see the 跟我们的6416演示程序关系比较大

  • CCIR Rec. 601 (last version is 601-2) specifies the the image format, acquisition semantic, and parts of the coding for digital "standard" television signals

  • CCIR-601 gives the specification for encoding of 4:2:2 signals and a tentative specification of 4:4:4 encoding. 4:2:2 means, that the color-difference signals Cr and Cb are sampled with half of the sampling frequency of the luminance signal Y, that is 13.5MHz to 6.75MHz. It also specifies the number of samples per line for 525/60(59,94) systems and 625/50 systems. The samples per total line are different, but the samples per active line are the same for both systems: 720 samples per active line


DM642-EVM single channel (using only channel A) of 8/10-bit BT.656 display, 8/10-bit raw video display, 16/20-bit Y/C video display, or 16/20-bit raw video display. Also, in the display mode of operation, the video port is capable of operating in a two-channel 8/10-bit raw mode in which two channels are locked to the same timing. For more details on the Video Port peripherals, see the 的配置要求

  • Code Composer Minimum Requirements

  • 233 MHz or faster Pentium or compatible

  • 600 Mb free hard disk space

  • 64 Mb free RAM

  • SVGA (800x600) color display

  • CD-ROM drive

  • Supported Operating Systems

  • Microsoft Windows 98. (SP1 and SE)

  • Microsoft Windows NT. (SP6)

  • Microsoft Windows 2000. (SP1 and SP2)

  • Microsoft Windows XP. (Home and Professional)


DM642-EVM single channel (using only channel A) of 8/10-bit BT.656 display, 8/10-bit raw video display, 16/20-bit Y/C video display, or 16/20-bit raw video display. Also, in the display mode of operation, the video port is capable of operating in a two-channel 8/10-bit raw mode in which two channels are locked to the same timing. For more details on the Video Port peripherals, see the 功能框图


DM642-EVM single channel (using only channel A) of 8/10-bit BT.656 display, 8/10-bit raw video display, 16/20-bit Y/C video display, or 16/20-bit raw video display. Also, in the display mode of operation, the video port is capable of operating in a two-channel 8/10-bit raw mode in which two channels are locked to the same timing. For more details on the Video Port peripherals, see the 功能特征

  • 32 Mb of SDRAM

  • 4 Mb of linear Flash memory

  • 2 video decoders

  • 1 video encoder

  • On-Screen Display FPGA implementation

  • Dual RS-232 UARTs and line drivers

  • AIC23 stereo codec

  • 10/100 Ethernet PHY

  • 32 Kb I2C EEPROM

  • 8 programmable LEDs

  • Numerous video inputs and outputs

  • Support for HDTV data rates


The heart of the DM642 EVM is a 600MHz DM642 Digital single channel (using only channel A) of 8/10-bit BT.656 display, 8/10-bit raw video display, 16/20-bit Y/C video display, or 16/20-bit raw video display. Also, in the display mode of operation, the video port is capable of operating in a two-channel 8/10-bit raw mode in which two channels are locked to the same timing. For more details on the Video Port peripherals, see the

Media Process which is based on TI’s successful line of

C64xx DSPs. The DM642 features a highly integrated onchip

peripheral set which includes 3 video port interfaces,

an I2C bus controller, a multi-channel serial audio port, 64-

bit EMIF, 10/100 Ethernet MAC controller and PCI interface

in addition to the high performance DSP core.

The DM642 EVM is designed to work with Code

Composer Studio (CCS) version 2.20.18 which is minor

upgrade to CCS 2.20 that adds support for newer C6000

family DSPs such as the DM642.

These patches are normally available through Code Composer’s on-line Update Advisor or on the web at http://dspvillage.ti.com but have been

included in the AddOns directory of the DM642 EVM CD-ROM for your onvenience.


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