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Electronics

Electronics. Status of the MEG Trigger system Status and plans for DAQ MSCB slow control system. The Trigger System of the MEG Experiment. On behalf of M. Grassi D. Nicolò F. Morsani S. Galeotti S. Giurgola . Expected Trigger Rate. Accidental background and

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Electronics

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  1. Electronics • Status of the MEG Trigger system • Status and plans for DAQ • MSCB slow control system

  2. The Trigger System of the MEG Experiment On behalf of M. Grassi D. Nicolò F. Morsani S. Galeotti S. Giurgola

  3. Expected Trigger Rate Accidental background and Rejection obtained by applying cuts on the following variables • photon energy • photon direction • hit on the positron counter • time correlation • positron-photon direction match The rate depends on RRe+ R2

  4. The trigger implementation Digital approach • Flash analog-to-digital converters (FADC) • Field programmable gate array (FPGA) Final system • Only 2 different board types • Arranged in a tree structure on 3 layers • Connected with fast LVDS buses • Remote configuration/debugging capability Prototype board Check of: • the FADC-FPGA compatibility • chosen algorithms • synchronous operation • data transmission

  5. The board type 0 control signals. LVDS transm. Differential drivers PMT inputs FPGA FADC LVDS receiv. configuration EPROMS package error solved with a patch board

  6. Circ. buff Circ. buff Circ. buff Circ. buff Diff. driver Proc. Algor. Fadc LVDS Tx Proc. Algor. LVDS Rx Circ. buff Circ. buff Prototype system configuration Board 1 input output 16 PMT Board 0 Diff. driver Proc. Algor. Fadc 16 PMT input Last BVR conclusions The prototype system met all requirements It is available to trigger the LP in future beam tests output LVDS Tx Proc. Algor. LVDS Rx Circ. buff Circ. buff LVDS in final

  7. Type2 Type2 Type2 Type2 Type2 Type2 . . . . . . . . . 20 boards 12 or 6 boards 10 boards Type1 Type1 Type1 Type1 Type1 Type1 Type1 Type1 Type1 4 4 4 16 16 16 4 x 48 4 x 48 20 x 48 10 x 48 12 x 48 Trigger system structure 2 VME 6U 1 VME 9U Located on the platform 2 boards LXe inner face (312 PMT) LXe lateral faces (208 PMT) (120x2 PMT) (40x2 PMT) 1 board 1 board 2 x 48 2 or 1 boards Timing counters (160 PMT) or (80 PMT)

  8. Diff. driver Fadc Proc. Algor. 16 PMT Circ. buff Circ. buff Circ. buff Circ. buff LVDS Tx Opt. Proces. Algor. LVDS Tx Circ. buff Type 1 LVDS Rx Proc. Algor. LVDS Rx 10 type1 LVDS Rx Type 2 LVDS Tx Opt. Proces. Algor. LVDS Tx Circ. buff

  9. Software items • New package ISE 6.2 • Verilog/schematic implementation • Block transfer in A32D16 format (VME library to be modified) Hardware items • JTAG programming/debugging through VME by modifying the Type0 • Analog receivers and with DACs for pedestal • FPGA selected: VirtexII PRO • On Type 1 XC2VP20-5-FF1152 • On Type 2 XC2VP40-5-FF1152 • Other components are fixed: • FADC • LVDS Tx and Rx • Clock distributor • Analog input by3M coaxialconnectors • LVDS connection by3M cables • Ancillary logic components and scheme

  10. FPGA • VIRTEX II - PRO • easily at 100MHz • 60% of IO • 40% of CLB • 2 PowerPC (not used)

  11. Analog receiver Differential driver DAC pedestal control AD8138 AD5300

  12. Analog receiver • 16 channels on a type1 board • 1 unit wide

  13. DC/DC converter • 1.5 Volts • 3.3 Volts

  14. ANCILLARY: TREE START ANCILLARY #0 TRIGGER VME STOP STOP SYNC CLK INT START, STOP, SYNC, CLK ANCILLARY #1 ANCILLARY #8 … (… 16) CLK EXT CLK EXT ………………………………

  15. ANCILLARY: BLOCKS TTL2LVDS INPUTS & CLK GEN CLK - START - STOP - SYNC VME INTERFACE 4 x 8(16)-LVDS-FANOUT 4 x SILICON DELAYS: START, STOP, SYNC, CLK

  16. ANCILLARY: INPUTS & CLOCK GEN INPUT CONNECTOR LVDS-to-TTL 10MHz CLK GEN INT/EXT SELECT

  17. ANCILLARY: SILICON DELAY

  18. ANCILLARY: LVDS FANOUT

  19. Trigger 2002 2003 2004 2005 Prototype Board Final Prototype Full System Prototype Board Final Prototype Full System part. inst. full. inst. Design Manufactoring Assembly Test Milestone

  20. summary • Components selected • Algorithms implemented • PCB design ready to start

  21. Status and plans for DAQ

  22. Domino Chip Principles Phase and Frequency Stabilization Trigger Signal Sampling domino wave FADC 8 inputs DLL Vspeed External Common Reference Clock shift register Low-jitter clock Freq. Cntr uC 16-bit DAC MUX

  23. Timing reference signal 20 MHz clock PMT hit Domino stops after trigger latency

  24. Recovery of Timing 4) Timing of all PMT pulses is expressed relative to t=0 point 1) Trigger publishes phase f of trigger signal f relative to clock in multiples of 10 ns f 50 ns 2) Each DAQ card determines and fits “Time-Zero-Edge” in clock signal and uses this as t=0 3) Measure pulse width of clock to derive domino speed Domino speed stability of 10-3 : 400ps uncertainty for full window 25ps uncertainty for timing relative to edge

  25. Current readout mode • First implemented in DRS2 • Sampled charge does not leave chip • Current readout less sensitive to cross-talk etc. R I Vin Vout read write . . . C

  26. DRS2 Chip • DRS2 design • Up to 4.5 GHz sampling speed • 8+2 channels, 1024 bins deep each • Readout speed up to 100 MHz (?) • Submitted to UMC in Nov. 18th, 58 chips received in Jan. 15th, packaging 3 weeks • DRS2 chip arrived in Feb. 04 • 50 packaged chips (400 channels) • 1.5 GHz – 4.5 GHz sampling speed • Current mode readout works • Jitter estimation: 40ps • Plans • VME prototype board by Aug. ‘04

  27. DRS2 chip

  28. DRS2 tests

  29. Sampling Speed Measurement • Obtained last week with USB-Mezzanine board • Usable sampling range 0.6 GHz – 4 GHz

  30. Jitter estimation • Oscilloscope triggered with Domino pulse • Show 250 turns later • 11ns/250 = 44ps • Should be improved with better board design

  31. Analog readout • 4 pulses, 12ns wide, ~1ns rise time digitized at 2.5 GHz • Readout at 40 MHz • Reproduced rise time: 1.2ns • Tests with FADC will follow

  32. VME boards with Mezzanine Cards R. Paoletti INFN Pisa MAGIC collaboration PSI GVME board

  33. PSI GVME Board

  34. VME Transition Boards • PMT/DC signals through front-panel connectors to CMC cards with DRS • Low-jitter clock through front-panel ch. #17 • Trigger, reset, etc through transition board • Read feedback to trigger thorough transition board Clock PMTs Clock

  35. DAQ System 800 + 160 area ~3m Trigger ~11m Active Splitter 3+1 VME crates PMT monitor trigger ready 5 VME crates ~3m optical fiber (~20m) DRS Board (32chn) + CPU Front-End PCs Rack – PC (Linux) SIS 3100 Rack – PC (Linux) Rack – PC (Linux) 1920 ~7m Rack – PC (Linux) DRS Board (32chn) + CPU DC Pre-Amp Rack – PC (Linux) Gigabit Ethernet backpressure Rack – PC (Linux) Rack – PC (Linux) Rack – PC (Linux) Raw data: 2880 channels 100 Hz 50% / 10% / 10% occupancy 2kB / waveform -> 5 x 25 MB/sec. Rack – PC (Linux) Rack – PC (Linux) Fitted data: 10 Hz waveform data -> 1.2 MB/sec 90 Hz ADC / TDC data -> 0.9 MB/sec Rack – PC (Linux) On-line farm storage

  36. Rack Layout Clock distribution (front) Trigger Board ready Fast clear Event counter (transition cards) ? Splitter Trigger DRS Interface Calo+TC DC

  37. HV HV DAQ Calo+TC Splitter Trigger DAQ DC

  38. Electronics in B-Field • B. Allongue (PH-ESS Group, Cern) • Wiener PL500 Power Supply works up to 300 Gauss (900 with water cooling) • Fan works up to 80-100 Gauss • Ordered “normal” crate for tests • Need air ducts with external A/C if problems arise [Gauss] Fringing field measured at πE5 4.2 6.8 9.1 6.7 18.5 83.8 50.5 9.0 33.5 433.7 440.3 31.2 7.5 20.4 73.3 56.3 69.7 19.8 7.8 11.6 11.3

  39. Waveform analysis Original Waveform • Zero suppression in FPGA • Single hit • ADC/TDC derived in FPGA • Multiple hit • Waveform compressed in FPGA (2x12 bit -> 3 Byte) • Waveform fitted / compressed in PC cluster • Store ADC/TDC only for “calibration” events • Store (lossless) compressed waveforms for MEG candidates Region for pedestal evaluation T integration area Difference Of Samples Threshold in DOS ADC2/TDC2 ADC1/TDC1

  40. Differential DRS channels cross-talk Vin • Measured for • 1ns rise-time: • 6% neighbor • 2% next nb write Vin + write Differential Driver signals cancel Vin -

  41. DRS3 • DRS2 can probably initially be used for DAQ (have 400 channels, can produce 400 more) • DRS2 limitations • Only two channels are fully differential (others show larger crosstalk) • Some tests remain to be done … • New DRS3 design • All channels differential • Additional shielding between channels (ground bond wires) • Reduced readout time (5x) minimized dead time • Internal cascading allows for n x 1024 sampling bins

  42. Plans • DRS2 VME prototype board Aug. 04 • Measure all parameters (cross-talk, resolution, stability) • Produce VME boards and equip with DRS2 chip (400 chn + 400 chn ?), install as much as possible in are in summer 2005 • Design DRS3 in parallel • Mass production of DRS3 in fall 2005 • Replace installed DRS2 with DRS3

  43. DRS (DAQ) 2002 2003 2004 2005 DRS1 Tests DRS2 2nd Prototype Boards & Chip Test DRS1 DRS2 Optional DRS2 production 400 chn DRS2 test board DRS3 Mass Production 400 chn 400 chn 3000 chn VME boards Full System installation Milestone Design Manufactoring Assembly Test

  44. Slow Control System • Unified control system for • Cryogenics (temperature, pressure, valves, etc.) • Environment (temperatures, crates) • Drift chamber gas system (pressure, mass flow, temperature) • High Voltage (Calo+TC+DC, ~1000 chn.) • System must be fail-safe

  45. PC 12:30 12.3 12:45 17.2 13:20 15.2 14:10 17.3 15:20 16.2 18:30 21.3 19:20 18.2 19:45 19.2 Slow Control HV Temperature, pressure, … Valves 12345 Terminal Server PLC RS232 GPIB ??? 15° C Ethernet heater MIDAS DAQ

  46. Slow Control Bus HV Temperature, pressure, … Valves heater MIDAS DAQ

  47. Field Bus Solutions • CAN, Profibus, LON available • Node with ADC >100$ • Interoperatibility not guaranteed • Protocol overhead • Local CPU? User programmable? • How to integrate in HV? (CAEN use CAENET)

  48. 8051-compatible mC with ADC 12-bit DAC 12-bit Flash EEPROM Timers Watchdog Temperature sensor UARTs Up to 100MHz clock speed External signal conditioning if needed Serial communication Hardware Overview

  49. RS-485 bus • Similar to RS-232 but • Up to 256 (1/8 load) units can be connected to a single segment, use repeater for more • Address space for 65536 nodes • single line, half duplex • differential twisted pair • Segment length up to km (20 m tested) • MSCB system: 115kbit • Single Master – Multiple Slaves (like USB) • Power through bus (10-wire flat ribbon) • PC USB interface

  50. Generic node SCS-200 • C8051Fxxx Micro controllers with 8x12 bit ADC, 2x12 bit DAC, digital IO, 8051 mC and 32kB Flash Memory • RS-485 bus over flat ribbon cable • Powered through bus • Costs ~CHF 50 • Piggy back board for signal conditioning cards • 32 kB for real time C programs

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