Procedure Hopping: a Low Overhead Solution to Mitigate Variability in Shared-L1 Processor Clusters
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Procedure Hopping: a Low Overhead Solution to Mitigate Variability in Shared-L1 Processor Clusters. Abbas Rahimi ‡ , Luca Benini † , and Rajesh Gupta ‡ ‡ CSE, UC San Diego † DEIS, Università di Bologna. http:// micrel.deis.unibo.it. http://variability.org . http://mesl.ucsd.edu.

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Http variability org

Procedure Hopping: a Low Overhead Solution to Mitigate Variability in Shared-L1 Processor Clusters

Abbas Rahimi‡, Luca Benini†, and Rajesh Gupta‡

‡CSE, UC San Diego

†DEIS, Università di Bologna

http:// micrel.deis.unibo.it

http://variability.org

http://mesl.ucsd.edu

International Symposium on Low-Power Electronics and Design 


Procedure hopping to mitigate variability

Main Point

Procedure Hoppingto Mitigate Variability


Http variability org

Sources of Device Variation

  • 10% VCC, ~160˚C Temperature, 40% VTH Variations are more challenging in a many-core platform!

guardband

actual circuit delay

Clock

Other

uncertainty

Across-wafer Frequency

Temperature

VCC Droop


Http variability org

Sources of Variations

Variation-tolerant Shared-L1 Processor Cluster

Process Variation → Variation-aware VDD-hopping

Dynamic Voltage Variation → Procedure hopping

Methodology for PLV

Design time characterization

Compile time PLV metadata generation

Runtime preventive compensation

Experimental Results

Outline


Http variability org

Each cluster consists of:

16 LEON-3 cores

An intra-cluster shared-L1I$

An on-chip multi-banked tightly coupled data memory (TCDM)

Two single-cycle logarithmic interconnections for both instruction and data sides

A hardware synchronization handler module (SHM) to coordinate and synchronize cores for accessing shared data on TCDM.

VDD-hopping per core.

Shared-L1 Processor Clusters *

Shared-L1 TCDM cluster template

4x8 cluster: 4 PEs and an 8-bank TCDM

* D. Melpignano, L. Benini, et al., “Platform 2012, a many-core computing accelerator for embedded SoCs: performance evaluation of visual analytics applications”, DAC’12


Http variability org

 Three cores (f4, f8, f9) cannot meet the target frequency of 830MHz.

  • VDD–hopping to Compensate Process Variation

VDD = 0.99V

VDD = 0.81V

VA-VDD-Hopping=(

,

0.81V

0.99V

)

 All cores of the same cluster meet the target frequency of 830MHz.

 VA-VDD-hopping can accordingly tune the cores' voltage based on their delay reported by CPMs.


V dd hopping to compensate process variation

VDD–hopping to Compensate Process Variation

  • The process variation is compensated 

  • but, cluster will have various Voltage/Temperature-islands!

Each core increases voltage if its delay is high.

  • Every core have its own voltage domain

  • All cores work with the same frequency

  • VDD-hopping tunes the voltage of each core based on CMP.


Http variability org

The IR-drop of execution of FIR on cores with various operating corners.

FIR does not face any voltage emergency (IR-drop < 4%) at the corners with voltages of 0.81V-0.9V due to their lower power densities.

Fast Dynamic IR-drop within Cluster


Procedure hopping to compensate voltage variation

Procedure hopping to Compensate Voltage Variation

Each procedure hops from one core to another if it causes voltage variation.

Procedure hopping facilitates fast and proactive migration of procedures within a cluster to prevent voltage variation thanks to shared I$ and TCDM resources.


Http variability org

Sources of Variations

Variation-tolerant Shared-L1 Processor Cluster

Process Variation → Variation-aware VDD-hopping

Dynamic Voltage Variation → Procedure hopping

Methodology for PLV

Design time characterization

Compile time PLV metadata generation

Runtime preventive compensation

Experimental Results

Outline


Procedure level vulnerability plv

Procedure-level Vulnerability (PLV)

The notion of PLV to fast dynamic voltage variation is defined.

The design time stage analyzes the dynamic voltage droops/rises for every ProcX under full operating conditions  generating PLVx metadata.

Observe IR-drops

int ProcX (…) {

}

(Vi,Tj)

Corei


Characterization of plv to ir drop compile time runtime

Characterization of PLV to IR-drop: Compile time + Runtime

At compile time, PLVx metadata of ProcX is attached to the procedure.

During runtime, the discretized (V,T) point to the corresponding characterized PLVmetadata to assess the vulnerability of ProcX at the current (V,T).

If PLVx ≥ PLV_threshold, the ProcX will be hopped from caller core to a favor callee core.


Http variability org

Sources of Variations

Variation-tolerant Shared-L1 Processor Cluster

Process Variation → Variation-aware VDD-hopping

Dynamic Voltage Variation → Procedure hopping

Methodology of PLV

Design time characterization

Compile time PLV metadata generation

Runtime preventive compensation

Experimental Results

Outline


Max voltage variation across corners and procedures

Max Voltage Variation Across Corners and Procedures

Most of procedures running at cores with 0.99V have voltage emergencies.

At 0.9V, only four procedures (IFFT, IDCT, matrix, ttsprk) face the voltage emergencies.

No voltage emergency at 0.81V.

Max voltage droop (%)

  • Procedure hopping avoids the voltage emergency for all procedures by hopping them form a high-voltage core to a low-voltage core.


Cost of procedure hopping

Cost of Procedure Hopping

The total roundtrip overhead of the hopping a procedure from the caller core and returning the results from the callee core is less than 800 cycles.

This overhead is less than 1% of the total cycles needed to execute any of the characterized procedures in EEMBC benchmark.

During the procedure hopping no voltage emergency can occur even at (0.99V,125˚C), neither in the caller nor the callee core.


Conclusion

Conclusion

The notion of procedure-level vulnerability to fast dynamic voltage variation is defined.

Based on PLV metadata, a fully-software low-cost procedure hopping technique is proposed which guarantees the voltage emergency-free migration of all procedures, fast and proactively enough within a shared-L1 processor cluster.

Full post-P&R results in 45nm TSMC technology confirms that the procedure hopping avoids the voltage emergency across a variability-affected cluster, while imposing only an amortized cost of less than 1% latency for any of the characterized embedded procedures.


Http variability org

Thank you!

  • Acknowledgment

  • NSF Variability Expedition

  • ERC Multitherman Project

http://variability.org


Hw sw collaborative architecture to support intra cluster procedure hopping

HW/SW Collaborative Architecture to Support Intra-cluster Procedure Hopping

The code is easily accessible via the shared-L1 I$.

The data and parameters are passed through the shared stack in TCDM.

A procedure hopping information table (PHIT) keeps the status for a migrated procedure.


Intra procedure peak power variation

Intra-procedure Peak Power Variation

Maximum of 1.28× intra-corner peak power variation occurs between IFFT and tblook procedures at (0.81V,125C).

Maximum inter-corner peak power variation is 3.5× for FIR.

Maximum of 4.1× peak power variation across corners and procedures, a2time at (0.81V,-40C), and IFFT at (0.99V,125C).


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