Pcie 2 0 base specification protocol and software overview
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PCIe 2.0 Base Specification Protocol And Software Overview. Dave Harriman and Joe Cowan PCIe Protocol and Software Workgroups. Today’s Topics. Introduction Overview of changes Completion Timeout ECN Function Level Reset ECR 2.0 base spec link speed controls Link Bandwidth Notification ECR

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Pcie 2 0 base specification protocol and software overview

PCIe 2.0 Base Specification Protocol And Software Overview

Dave Harriman and Joe CowanPCIe Protocol and Software Workgroups


Today s topics

Today’s Topics

  • Introduction

  • Overview of changes

  • Completion Timeout ECN

  • Function Level Reset ECR

  • 2.0 base spec link speed controls

  • Link Bandwidth Notification ECR

  • Access Control Services ECR

  • Trusted Config Space ECN


Introduction

Introduction

Q1 06

Q2 06

Q3 06

  • PCI-SIG updating PCI Express (PCIe) specifications this year

  • Single largest change – 5gigabit/second (Gb/s) signaling speed

    • Optional new capability

  • Several other improvements

Base

.7

.9

2.0

Today’s focus


Overview of changes

Overview Of Changes

  • Engineering Change Requests (ECRs),Engineering Change Notices (ECNs), and Errata

    • ECRs become ECNs after review/approval

    • All ECNs and Errata included in 2.0 publication

  • Errata – highlights

    • Root Complex Event Collector Base Class Code conflict

    • Clarifications of uncommon error cases

    • Register bit clarifications on defaults, implementation requirements

    • Interrupt disable bit consistency with conventional PCI

  • 5Gb/s signaling speed not an ECN

    • Included only in 2.0


Completion timeout ecn

4s to 64s

250ms

to 4s

10ms

to 250ms

50us

to 10ms

Completion Timeout ECN

  • Required: Architected disable bit

    • “Turns off” timeout

    • Not to be used in normal operation

  • Optional Completion Timeout time value programmability

    • Devices indicate supported ranges from the four bins defined

    • Two selectable ranges for each bin


Function level reset flr ecr

Function Level Reset (FLR) ECR

  • Background: New type of reset

    • Existing resets may (but not required to) reset function internals

    • FLR definition requires function internal reset

  • General concept: SW initiated function-specific reset

RESET “FAMILY TREE”

Conventional

FLR

Cold / Warm

(PERST#)

Hot

S.B.R.


Function level reset flr ecr1

Function

Reset

F0

F1

F2

PCIe

Endpoint

Function Level Reset (FLR) ECR

  • Endpoints only

    • All types: Legacy, Native, Integrated

  • Register interface simple

  • Implementation and effects potentially complex

    • Resets internal function-specific state

  • Not all architected registers are reset

    • Hardware Initialized (HwInit), BIOS set, etc.


2 0 base link speed controls external link speed management model

2.0 Base Link Speed ControlsExternal link speed management model

  • By default, hardware automatically trains to the greatest common speed

    • Software can set an upper bound on the speed

    • Hardware can always limit speed for Link reliability

  • By default, hardware is permitted to change the speed autonomously for other purposes, suchas power management

    • Software can disable this

  • There is a new mechanism supporting software control for entering/exiting Compliance Mode


2 0 base link speed controls new modified regs for external links

2.0 Base Link Speed ControlsNew/modified regs for external links

  • Link capability register

    • Maximum Link Speed field renamed to Supported Link Speeds

  • Link Status register

    • Link Speed field renamed to Current Link Speed

  • (new) Link Control 2 register

    • Target Link Speed field

    • Hardware Autonomous Speed Disable bit

    • Enter Compliance bit


2 0 base link speed controls root complex internal links

2.0 Base Link Speed ControlsRoot complex internal links

  • Can report their supported and current speeds via similar changes to their Capability and Status registers

  • Speed is not controllable via architected mechanisms


Bandwidth notification ecr general

Bandwidth Notification ECRGeneral

  • Motivation

    • Need mech for PCIe-aware software to be notified whenLink bandwidth (speed or width) changes, due to hardware-autonomous link retraining

    • Can help reduce vendor support costs by having software notify users if marginal links retrain to a lower bandwidth, impacting system performance

    • Want it available ASAP for all new PCIe components, not just those supporting 5 Gb signaling

  • Though specified in separate document, still logically coupled with link speed controls

  • ECR timing is somewhat tied to link speed controls stabilizing

  • Plan to make this a mandatory featurefor PCIe Base 2.0 (optional for 1.1)


Bandwidth notification ecr mechanism details

Bandwidth Notification ECRMechanism details

  • Link capability register

    • Link Bandwidth Notification Capability bit

  • Link control register

    • Hardware Autonomous Width Disable bit

    • Link Bandwidth Management Interrupt Enable bit

    • Link Autonomous Bandwidth Interrupt Enable bit

  • Link status register

    • Link Bandwidth Management Status bit

    • Link Autonomous Bandwidth Status bit


Access control services ecr general

Access Control Services (ECR)General

  • Set of access control services for downstream portsand functions in multi-function devices

  • New extended capability and status/mask/severitybits in AER

  • Source validation – downstream Ports range check Requester ID BusNum in upstream Request TLPs

  • Peer-to-peer controls determine whether to forward directly, block, or redirect peer-to-peer Request TLPsto the RC for access validation

  • Controls being considered for functionality definedby the Address Translation Services ECR


Access control services ecr details

Applicable to

Root Complexes

Switches

Multi-function devices

Planned services

Source Validation

P2P Redirect & Upstream Forwarding

P2P Egress Controls

Translation Blocking (ATS)

Direct Translated P2P (ATS)

Access Control Services ECRDetails

CPU

Root Complex

Memory

Switch

MFD 1

End

point

2

End

point

3

End

point

4

Fn0

Fn1


Trusted config space ecn

ECR presented in detail at WinHEC 2005

Final ECN completed in July 2005

No significant changes before finalized

Trusted Config Space ECN


Call to action

Call To Action

  • Comprehend Upcoming PCIe 2.0 Base spec improvements

    • Many enhancements in 2.0 besides 5 Gb/s signaling speed

  • Start planning your 2.0 product now

  • Keep in-sync with PCI-SIG for further updates


Additional resources

Additional Resources

  • Web resources: http://www.pcisig.com

    • Specs, white papers, and more


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