A 1.8V 1.6GS

1. A 1.8V 1.6GS/s 8b Self-Calibrating Folding ADC with 7.26 ENOB at Nyquist Frequency  Robert Taft, Chris Menkus, Maria Rosaria Tursi, Ols Hidri, Valerie Pons National Semiconductor GmbH, Fürstenfeldbruck, Germany

2. Outline of Presentation High-Speed ADC Applications Architecture Comparison Folding ADC with Calibration Measurement and Results Conclusion

3. Set-Top Box Receivers Digital Video Broadcast (DVB) Digitizing Oscilloscopes ATE Systems Radar / SIGINT Applications

4. Set-Top Boxes In the system on the right, multiple channels are tuned digitally. Spurious-free dynamic range is the critical performance parameter.

5. Digitizing Oscilloscopes In an oscilloscope, parameters such as bit-error-rate (BER) and pulse response are important. The ADC input bandwidth should be large to allow for repetitive sampling.

6. Electromigration Line Width ? Capacitance ? Power Temperature aggravated Gate Oxide Overvoltage Protection circuitry Hot Electron Effects Offset drift due to bias High Speed Design Challenges

7. Nyquist CMOS ADC Architectures Folding and Flash suited to high-speed due to no decision feed-back loops. Folding better suited than Flash to high resolution, because fewer comparators & encoding signals required. Calibration enhances folding speed / resolution.

8. Schematic for a 2-bit flash converter, which uses a resistor ladder to subdivide end-point reference voltages VRT and VRB. The binary encoded output is “10”. Flash ADC

9. Flash ADC With Pre-Amplifiers

10. In a “by-N” folding amplifier stage, the outputs of N amplifier stages are summed with opposing signs at a single load point. (van der Plassche, JSSC 1979). A separate flash “coarse” ADC determines which region the input signal was in. Folding

11. Folding (cont.)

12. Example of Folding (Order, k = 3) 21 parallel input amplifiers of a Flash ADC are grouped into widely spaced triplets (one triplet is shown). The two amplifiers not involved in a decision are saturated, and don’t influence the comparator.

13. Example of Folding (cont.) The output signal has been folded. Three detectable zero-crossings are at the desired values of VR,1 VR,8 and VR,15. Therefore, the number of “fine” comparators has been reduced by 3X. In this work, 3X folding at the 2nd and 3rd bank of preampliers results in the order k = 3x3 = 9 reducing the 257 normally required “fine” comparators by 9X! 7 “coarse” comparators locate which of the nine folds the input signal was in—no decision feedback loop! Folding increases sensitivity to offsets.

14. Folding ADC with Calibration

15. Calibrated Folding-Interpolating ADC

16. Constant-Vgs MUX The high-bandwidth, low-distortion input-MUX gate is low power and has nearly constant-VGST (body effects of M and N nearly cancel, P has no body effect). In contrast, a conventional constant-VGS switch is used for sampling in the Track&Hold.

17. Sample and Hold

19. Reductions Of ENOB By Samplig Clock Jitter

20. Timing Skew in Interleaved Converters Output spectrum has tone at Fs/2 - Fin Similar picture for gain mismatch. Static offset gives tone at Fs/2.

21. Master Sampling Clock Interleaved sampling requires tA < 1 ps skew between channels. Low skew achieved with a master sampling clock (Nagaraj, ISSCC 2000) & exacting layout: Step-and-repeat & cell mirroring. Measured tA < 0.35 ps (peak-peak) at FIN = 1.5 GHz, using the FS / 2 - FIN spur (PtA) with equation:  PtA (dB) = 20 log10 (2? FIN tA,RMS)  

24. Positive and negative kickback to reference ladder cancel to first order.

25. Averaging In an array, averaging reduces the effect of an amplifier’s offset by making its output the superposition of its own and neighboring amplifier’s outputs. (Kattman, ISSCC 1991) The amount of averaging is determined by the number of amplifiers in the array that are active (ie. not saturated) for a given input. Each amplifier output is coupled to its neighbor through resistors. The smaller the resistance between two amplifier outputs, the more the amplifiers influence each other.

26. Averaging (cont.)

27. Calibration For high speeds, offsets can’t be decreased by arbitrarily increasing transistor size (?VT ? 1 / ? W L). Calibration allows increasing resolution and speed. Best design practices minimized the offset error prior to calibration. This reduces the offset correction range required: ~ 10X improvement target in INL. This allows stable one-time calibration.

28. Calibration (cont.) Series resistors between amp1 and amp2 allow the calibration adjustment to have a localized and averaged component. Cascaded Amp1 and Amp2’s are calibrated together, despite having very different averaging.

29. Calibration (cont.) During calibration, NC comparator outputs determine the ICAL1,2,.. adjustments, while VIN is stepped with a linear on-chip resistor. The amplifier zero-crossings are folded onto comparator zero-crossings, resulting in a minimum NC = NA / k.

30. Folding Amplifiers Only one of the three amplifiers on the same amp2 folding bus “makes the decision”. The large amplifier separation results in a large capacitance on the folding bus. To mitigate the effect of a large folding-bus capacitance, a folded cascode output is used. Power penalty is small. Stage is high gain.

31. “Hybrid” Comparator

32. Regenerative Loops

33. Bit Error Rate (BER) In an Analog to Digital Converter (ADC) the comparator decides whether an input voltage is larger or smaller than a reference voltage. The comparator output is a logic 1 or 0, depending on the result of the comparison. The difference between input and reference voltage must be sufficiently large for the regenerative loop of the comparator to resolve this differential input in the allotted comparison time. For certain small differential inputs, the comparators and following bistable circuits will not produce well defined logic levels during the comparison period. This ambiguity, or metastability, is a dominant source of bit errors. The probabilty of this event to occur is exponentially proportional to the alloted regeneration time of the analog signal in input to the comparator latch.

34. BER Measurements

35. BER Conclusions The cascading of low time-constant bistable devices prior to encoding leads to an extremely low BER for the ADC08D1000. Therefore, the BER of this converter could not be simulated at 1 GSPS except by extrapolation from higher conversion speeds. The BER is a strong function of simulation corner. The typical ADC08D1000 BER is 10-35 in the typical simulation corner, 1.8 V and 90 C, including layout parasitics. That is, the possibility for a many LSB error to occur due to comparator metastability is once in every 1035 clock cycles or 1018 years. The guaranteed BER is 10-24 (once every 107 years). This value of for the worst corner (Slow MOS, layout parasitics, high temperature (130 C) and low supply voltage 1.8V).

37. Measurement and Results

38. Evaluation Board

39. Clock And Data Inputs:Balun Transformer

40. Measured DNL & INL

41. Measured FFT Spectrums

42. Measured ENOBs vs FIN @ 1.6 GSPS

43. Measured Pulse-Response 1.8 V, 1.6 GSPS, VIN = 1 MHz, 0.70 VDIFF Squarewave.

44. Measured Pulse-Response (zoom) 1.8 V, 1.6 GSPS, VIN = 1 MHz, 0.70 VDIFF Squarewave.

45. Measured 800 MHz Beat-Frequency 1.8 V, 810 MSPS, VIN = 810.7 MHz, 0.70 VDIFF Squarewave.

46. Measured 1.6 GSPS Beat-Frequency 1.8 V, 1.6 GSPS, VIN = 1.6026 GHz, 0.70 VDIFF Square / Sinewave.

47. Performance Summary at 1.6 GSPS

48. Calibration in combination with best practice design enables a large jump in sample rate and performance. Timing jitter will be the limiting factor in future higher-speed ADCs. Process reliability issues increasingly important. Conclusions

49. A 1.8V 1.6GS/s 8b Self-Calibrating Folding ADC with 7.26 ENOB at Nyquist Frequency  Ols Hidri ols.hidri@nsc.com

50. THD Limit of a ADC