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CS231 (Fall 05) Review Session. Sangkyum Kim Dec 2, 2005. Outline. Administrative Information. Control Unit. Other DataPath designs. MP4. Administrative Information. HW7 Due 12/5 Mon 5:00 pm MP4 Due 12/9 Fri 5:00 pm Final Exam Time: 12/15 Thu 8:00 – 11:00 am

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CS231 (Fall 05) Review Session

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Cs231 fall 05 review session

CS231 (Fall 05)Review Session

Sangkyum Kim

Dec 2, 2005


Outline

Outline

  • Administrative Information

  • Control Unit

  • Other DataPath designs

  • MP4


Administrative information

Administrative Information

  • HW7

    • Due 12/5 Mon 5:00 pm

  • MP4

    • Due 12/9 Fri 5:00 pm

  • Final Exam

    • Time: 12/15 Thu 8:00 – 11:00 am

    • Place: TBD (SC 1404 + 1 more)


Outline1

Outline

  • Administrative Information

  • Control Unit

  • Other DataPath designs

  • MP4


Harvard architecture

ADRS

Instruction

RAM

OUT

ADRSDATA

Data RAM

OUT

MW

Harvard Architecture


Block diagram of a processor

Program

D data

WR

Write

PC

DA

D address

Control signals

Register File

Branch

Control

Control

Unit

V

C

N

Z

Datapath

ADRS

Instruction

RAM

OUT

Status signals

AA

A address

B address

BA

A data

B data

Constant

RAM

MB

ADRS

DATA

OUT

S D1 D0

Q

+5V

CS

MW

WR

B

A

Instruction Decoder

FS

FS

V

ALU

C

N

Z

DAAABAMBFSMDWRMW

D0

F

Q D1

S

MD

Block diagram of a processor


Control unit

Branch

Control

V

C

N

Z

PC

PC

Branch

Control

ADRS

Instruction

RAM

OUT

V

C

N

Z

ADRS

Instruction

RAM

OUT

PL JB BCAD

Data

Data

Load

Load

PC

PC

Instruction Decoder

Instruction Decoder

Instruction Decoder

ADRS

Instruction

RAM

OUT

ADRS

Instruction

RAM

OUT

DAAABAMBFSMDWRMW

DAAABAMBFSMDWRMW

DAAABAMBFSMDWRMW

Control Unit


The whole processor

D

Register file

A B

WR

DA

AA

BA

Branch

Control

V

C

N

Z

constant

PC

1 0

Mux B

MB

ADRS

Instruction

RAM

OUT

ADRSDATA

Data RAM

OUT

FS

AB

ALU

G

MW

V

C

N

Z

Instruction Decoder

DAAABAMBFSMDWRMW

0 1

Mux D

MD

The whole processor

Control Unit

Datapath

(to the datapath)


Cs231 fall 05 review session

D

Register file

A B

WR

DA

AA

BA

Branch

Control

V

C

N

Z

constant

PC

1 0

Mux B

MB

ADRS

Instruction

RAM

OUT

ADRSDATA

Data RAM

OUT

FS

AB

ALU

G

MW

V

C

N

Z

Instruction Decoder

DAAABAMBFSMDWRMW

0 1

Mux D

MD


Cs231 fall 05 review session

D

Register file

A B

WR

DA

AA

BA

Branch

Control

V

C

N

Z

constant

PC

1 0

Mux B

MB

5

ADRS

Instruction

RAM

OUT

FS

ADRSDATA

Data RAM

OUT

FS

AB

ALU

G

MW

V

C

N

Z

Instruction Decoder

DAAABAMBFSMDWRMW

3

3

3

0 1

Mux D

MD

DA

AA

BA

MB = I15 WR = I14’ + I15’ I13

MD = I14 MW = I15’ I14 I13’

3


Quiz 1

(Quiz 1)

  • Give the 16 bit machine code for following instructions and also give the specified control signal.

    • ADD R3,R2, 2

    • LD R2, (R3)

    • ST (R4), R5

Machine Code: 100 0010 011 010 010

FS: 00010 MB: 1 MD: 0 WR: 1 MW: 0

Machine Code: 011 xxxx 010 011 xxx

MD: 1 WR: 1 MW: 0

Machine Code: 010 xxxx xxx 100 101

MB: 1 WR: 1 MW: 0


Quiz 11

(Quiz 1)

  • Give the 16 bit machine code for following instructions and also give the specified control signal.

    • ADD R3,R2, 2

    • LD R2, (R3)

    • ST (R4), R5

Machine Code: 100 0010 011 010 010

FS: 00010 MB: 1 MD: 0 WR: 1 MW: 0

Machine Code: 011 xxxx 010 011 xxx

MD: 1 WR: 1 MW: 0

Machine Code: 010 xxxx xxx 100 101

MB: 1 WR: 1 MW: 0


Quiz 12

D

Register file

A B

WR

DA

AA

BA

constant

1 0

Mux B

MB

ADRSDATA

Data RAM

OUT

FS

AB

ALU

G

MW

V

C

N

Z

0 1

Mux D

MD

(Quiz 1)

  • Give the 16 bit machine code for following instructions and also give the specified control signal.

    • ADD R3,R2, 2

    • LD R2, (R3)

    • ST (R4), R5

Machine Code: 100 0010 011 010 010

FS: 00010 MB: 1 MD: 0 WR: 1 MW: 0

Machine Code: 011 xxxx 010 011 xxx

MD: 1 WR: 1 MW: 0

Machine Code: 010 xxxx xxx 100 101

MB: 1 WR: 1 MW: 0


Cs231 fall 05 review session

5

3

3

3

FS

BC

AD

AD

PL

JB

0

X

0

X

0

X

3

3

3

0

X

0

X

DA

AA

BA

0

X

1

0

1

1

PL

JB

Instruction

0

x

Other

1

0

Branch

1

1

Jump

MB = I15 WR = I14’ + I15’ I13

MD = I14 MW = I15’ I14 I13’

3

PL = I15 I14 JB = I13

3


Cs231 fall 05 review session

Branch

Control

V

C

N

Z

D

Register file

A B

PC

WR

DA

AA

BA

ADRS

Instruction

RAM

OUT

constant

PL JB BCAD

1 0

Mux B

MB

5

3

3

3

FS

ADRSDATA

Data RAM

OUT

BC

AD

AD

FS

AB

ALU

G

MW

V

C

N

Z

Instruction Decoder

DAAABAMBFSMDWRMW

3

3

3

0 1

Mux D

MD

DA

AA

BA

MB = I15 WR = I14’ + I15’ I13

MD = I14 MW = I15’ I14 I13’

3

PL = I15 I14 JB = I13

3


Quiz 2

(Quiz 2)

  • Give the 16 bit machine code for following instructions and branch control inputs and outputs.

    • BNZ R3, -3

    • JMP 5

Machine Code: 110 x111 111 011 101

PL: 1 JB: 0 BC: 111 AD: 111101

Machine Code: 111 xxxx 000 xxx 101

PL: 1 JB: 1 AD: 000101


Quiz 21

Condition

BC

If carry set

000

If negative

001

If overflow

010

If zero

011

If carry clear

100

If positive

101

If no overflow

110

If non-zero

111

(Quiz 2)

  • Give the 16 bit machine code for following instructions and branch control inputs and outputs.

    • BNZ R3, -3

    • JMP 5

Machine Code: 110 x111 111 011 101

PL: 1 JB: 0 BC: 111 AD: 111101 PC: 1

Machine Code: 111 xxxx 000 xxx 101

PL: 1 JB: 1 AD: 000101 PC: 1


Outline2

Outline

  • Administrative Information

  • Control Unit

  • Other DataPath designs

  • MP4


Problem with our datapath

Problem with our Datapath

  • Other than the obvious: need more registers, more bits in each register (and therefore in datapath)

  • The clock cycle time is constrained by the longest possible instruction execution time.

  • Solution:

    • break an instruction execution into multiple cycles

    • Microprogrammed datapath, Pipelined datapath


Microprogrammed datapath

Microprogrammed datapath


Pipelining

Pipelining


Simple 5 stage pipeline

Simple 5-stage Pipeline


Outline3

Outline

  • Administrative Information

  • Control Unit

  • Other DataPath designs

  • MP4


Cs231 fall 05 review session

THANK YOU!


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