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Status of the digital readout electronics

Status of the digital readout electronics. Mauro Raggi and F. Gonnella LNF Photon Veto WG CERN 13/ 1 2/2011. New lab, a new collaborator, a new paper! The wiener crate LAV FEE Basic tests of the crates Reprogramming crate voltages The status of the TELL1 readout system in Frascati.

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Status of the digital readout electronics

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  1. Status of the digital readout electronics Mauro Raggiand F. Gonnella LNF Photon Veto WG CERN 13/12/2011

  2. New lab, a new collaborator, a new paper! • The wiener crate LAV FEE • Basic tests of the crates • Reprogramming crate voltages • The status of the TELL1 readout system in Frascati OUTLINE

  3. New LAV electronic lab at LNF Proceedings of twepp available on ArXiv The lab is equipped with: A NIM and CAMAC crates A commercial VME 6U Daq system (based on HPTDC) A custom LAV FEE 9U crate + 1TELL1 and 2 TDCb V5 A LAV FEE 9U prototype board We have a new 2 year post doc collaborator: F. Gonnella

  4. LAV readout chain Each LAV FEE boards Get 32 analog inputs and produce 64 LVDS outputs The output is sent to the TDC using 2 custom SCSI2  HDCI cables

  5. The LAV 9U FEE board 1 2 4 Operating voltage ±12V reduced to ±7.5V by onboard voltage regulators 3 4 3

  6. Test of the NA62 FEE TEL62 crates

  7. The LAV 9U crate With respect to standard TELL1 crates 46A of a voltage in the range 7-16 has been added. The current Wiener setting we have the voltage set to ±12V for the LAV line. Being the only user of the line we are free to change the value in the range 7-16V.

  8. The TELL1 into LAV crate BUG Crate Power supply TEL62 J1 TELL1 J1 connector TELL1 J1

  9. Basics tests • We performed very basic set of tests on the FEE TEL62 crates. • Mechanical test is ok • Electrical test of power supply is ok for both the TELL1 and FEE boards • Preliminary noise tests: • we checked that there is no noise transfer between TELL1 and the FEE • Same level of noise in the FEE with or without TELL1 in the crate • No additional noise when accessing the TELL1 using CCPC connection • We checked that the noise in the FEE depends on the crates power supply • Increase the current load to the crate power supply • Try a new test with V = ±7.5 V to increase the drop on linear regulators External power supply Wiener crate power supply 1,7 ms 2mV 0.5ms 7mV

  10. Hacking the LAV crate To save power the LAV FEE can be operated at ±7V instead of the ±12V just removing the regulators and reprogramming the LAV crate to provide ±7V. Crate is protected against the use of non standard power supply voltage need to reprogram a ROM inside the crate Reprogramming LAV crate by steps Construct dongle Enable rom access Download PC program UEP6000.exe Restart Crate Set new voltage and new defaults using wiener program Connect to WINXP Pc with an RS232 port

  11. First LAV readout cell! Connection of LAV FEE to TDC just like it will be at the experiment! Doing the full readout is only adding more FEE and TDCb and routing cables Cable routing studied has to start to validate cable length before final production DAQ test is planned for January next year: Pulse 32 ch FEE inputs read them out with Tell1

  12. A FC11 based pc has been setup as server for the TELL1 • Different from standard version with SL4 - SL5 • Few problems with setup of the CCPC due to DHCP settings sitting in different directory in FC11 wrt scientific linux • The CCPC now boots successfully • The TDSPY program is running on the CCPC • TDSPY scripts currently interacting well with the TELL1 FPGA and TDCb: • FPGA status read and write are all OK • TDCb Mezzanine on/off • TDCb tested successfully • Clock provided successfully with AGILENT 81110A • Clock frequency used 40.080 MHz TELL1 CCPC server installation

  13. 2 persons involved in preparing a firmware for the LAV • Mauro Raggi (LNF) • Francesco Gonnella (LNF, brand new postdoc) • A computer (dual core, XEON 3.1GHz, 2Gbyte RAM) running WIN7 has been setup for firmware development • The last version of the TELL1 firmware has been setup, compiled, synthesized • The firmware (.pof file) has been uploaded to the TELL1 using the ROM LAV firmware

  14. Software installed All tools are installed: Mentor GraphicsHDL Designer Altera QuartusII v. 11 • Run under Windows seven • Still to install SVN in local PC. Only works from LXPLUS

  15. DDR II memory PP-FPGA firmware DDR control Data extraction Data formatter and writer From SL FPGA Trigger handling TDCb Data correction TDCbcomm Trigger primitivegenerator Core services & monitoring LAV specific Inter-PPcommunication Prev PP Next PP

  16. SL-FPGAFirmware QDR QDR control Gbithandling To Gbit Eth Data formatter and writer Data merger Core services & monitoring Trigger primitivemerger PP0 PP1 PP2 PP3 Trigger primitivehandling TTCrx & trigger handling AUX boardcommunication LAV specific From TTCrx Prev TEL62 Next TEL62

  17. Plans • Try do run data acquisition with present tell1 firmware • Still need some study of the daq software • Start developing a stand alone version of the LAV firmware • Start with the development of the data correction module • Produce an independent test bench with proper simulated inputs • Decide in which FPGA we want to set the module

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