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Reduced Triple Modular Redundancy for Tolerating SEUs in SRAM based FPGAsPowerPoint Presentation

Reduced Triple Modular Redundancy for Tolerating SEUs in SRAM based FPGAs

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Vikram Chandrasekhar, Sk. Noor Mahammad, V. Muralidharan

Dr. V. Kamakoti

Department of Computer Science and Engineering

Indian Institute of Technology Madras, India

Dr. N. Vijaykrishnan

Department of Computer Science and Engineering

Pennsylvania State University, U.S.A.

MAPLD 2005

Reduced Triple Modular Redundancy for Tolerating SEUs in SRAM based FPGAsOutline of the talk

- Single Event Upsets (SEUs) in FPGAs
- Motivation
- Signal probability propagation for LUTs
- Sensitivity of LUTs
- Reduced Triple Modular Redundancy (RTMR)
- SEU simulator
- Experimental Results
- Conclusions

Single Event Upsets (SEUs)

- Circuit errors caused due to excess charge carriers induced primarily by external radiations
- Cause an upset event but the circuit itself is not damaged

SEUs in LUTs

- Single Event Upset changes the function stored in LUT
- Behavior of the circuit configured on to the FPGA is modified

SEUs in a Switch Matrix

Fault-free switch matrix

Deletion of a net

Formation of a new net

Two nets are shorted

Motivation

- TMR hardened design takes 200% extra area
- Certain logic blocks can halt the SEU propagation in the circuit
- Focus is on the Boolean network of LUTs obtained after technology mapping
- LUTs are more likely to stop SEUs rather than simple gates
- Lesser redundancy in LUTs is required compared to redundant gates

Signal Probability

- Probability that a line carries a value ‘1’
- Largely governed by the functions stored in the LUTs
- Can be used to estimate the value carried by a line
- The inputs are assigned random signal probabilities
- Input values are propagated along Boolean network to the primary outputs
- A threshold is fixed to get the expected value of a line from its signal probability

Signal Probability Propagation

- Calculation of signal probability of an LUT’s output is dependent on the stored function
- Signal probability of the LUT output is the probability of the input accessing a cell storing ‘1’
- Can be computed as a sum of probability products similar to the sum-of-products form of the function
- Let Mi {0,1}, for 1 i 4, and
V = F(M1, M2, M3, M4)

R(M1, P1) x R(M2, P2) x R(M3, P3) x R(M4, P4)

If V = 1

0

If V = 0

Where

B

If A = 1

R (M1, M2, M3, M4) =

1 - B

If A = 0

The output signal probability is defined as

MAPLD 2005

Signal Probability PropagationS (M1, M2, M3, M4) =

1 1 1 1

S (i, j, k, l )

i=0 j=0 k=0 l=0

Sensitive and Insensitive LUTs

- Input to an LUT can at most change by one bit - guideline for voter insertion
- Sensitive LUT - a change in any one of the expected input values changes the output
- Insensitive LUT - same value in all cells accessed due to a one-bit change in expected input
- Insensitive LUTs stop the SEU effect from propagating any further
- Form chains of sensitive LUTs that end at a voter followed by an insensitive LUT

Insensitive LUTs

Sensitive LUTs

Pseudo-insensitive LUTs

- A sensitive LUT whose fanouts are all insensitive LUTs
- An SEU effect passing through this LUT will not get past any of its fanouts
- Such an LUT need not be triplicated
- Cannot be treated as an insensitive LUT in identifying more pseudo-insensitive LUTs

Reduced Triple Modular Redundancy (RTMR)

- Assign random signal probabilities to primary inputs of the LUT network
- Propagate the signal probabilities through the network till the primary outputs
- Assign expected values to lines based on the threshold
- Mark LUTs as either sensitive or insensitive
- Find pseudo-insensitive LUTs and remark them
- Triplicate every sensitive LUT identified in the circuit

RTMR

- For every sensitive LUT L
- Triplicate L
- If all fanouts of L are sensitive LUTs
- Connect the fanout of each copy of L to the corresponding copies of the fanout LUTs

- Else
- Connect the fanout of each copy of the LUT to the corresponding copies of the fanout sensitive LUTs
- Insert a voter for the outputs of the three copies of the LUT
- Connect the output of the voter to all the fanout insensitive and pseudo insensitive LUTs

SEU Simulation

- For given technology mapping circuit
- A place and routing is performed using VPR tool
- Net adjacencies are generated from the routing to simulate possible bridge faults
- Using the technology mapping circuit, a Verilog model of the Boolean network is generated
- The delays of the nets between the LUTs are extracted from the routing provided by the VPR tool

Original Circuit

SEU Simulator

RTMR Circuit

Compare

Errors

MAPLD 2005

SEU SimulatorFaults

simulate

simulate

Fault generation

- A random fault list is generated which consists errors like
- Bridge Faults
- Nets disconnections
- Changes in the CLB SRAM cells

Simulation

- Each fault is simulated for a flexible duration of time to check the effectiveness of the RTMR circuit in tolerating the faults
- Bridge faults are most important because errors are propagated through multiple paths in the network
- Tougher to simulate since the RTMR circuit and the original circuit have different sets of possible SEU routing errors

Experimental Results

- Implemented on MCNC benchmark circuits to determine the required redundancy
- Threshold for signal probability was varied between 0.5-0.8 with nearly similar results
- Berkeley Logic Interchange Format (BLIF) files of the circuits are used for RTMR

No. of LUTs in original circuit

Percentage of sensitive LUTs

No. of LUTs in RTMR circuit

No. of LUTs in TMR circuit

apex4

1288

13.98

1648

3864

clma

13160

12.03

16326

39480

des

2155

36.2

3715

6465

diffeq

1875

29.98

2999

5625

elliptic

4181

15.48

5475

12543

ex5p

1162

35.46

1986

3486

frisc

5853

28.3

9166

17559

misex3

1477

18.15

2013

4431

pdc

5353

5.55

5947

16059

seq

1911

16.33

2535

5733

spla

3865

8.78

4544

11595

Tseng

1400

48.79

2766

4200

MAPLD 2005

Area overheads of RTMR vs. TMRConclusion and future work

- On an average, only 38% additional redundancy is required
- Insignificant loss of SEU immunity is observed using the SEU simulator
- Further study of the tradeoff between SEU immunity and LUT redundancy is required

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