ee2420 digital logic summer ii 2013
Download
Skip this Video
Download Presentation
EE2420 – Digital Logic Summer II 2013

Loading in 2 Seconds...

play fullscreen
1 / 20

EE2420 – Digital Logic Summer II 2013 - PowerPoint PPT Presentation


  • 108 Views
  • Uploaded on

EE2420 – Digital Logic Summer II 2013. Set 4: Other Gates. Hassan Salamy Ingram School of Engineering Texas State University. Other Logic Gates. NOT NAND – Not AND NOR - Not OR XOR - Exclusive OR XNOR - Equivalence function (X  Y). NOT. Not AND - Easy to build – only 2 gates!

loader
I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
capcha
Download Presentation

PowerPoint Slideshow about ' EE2420 – Digital Logic Summer II 2013' - iden


An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript
ee2420 digital logic summer ii 2013
EE2420 – Digital LogicSummer II 2013

Set 4: Other Gates

Hassan Salamy

Ingram School of Engineering

Texas State University

other logic gates
Other Logic Gates
  • NOT
  • NAND – Not AND
  • NOR - Not OR
  • XOR - Exclusive OR
  • XNOR - Equivalence function (X  Y)
slide3
NOT
  • Not AND - Easy to build – only 2 gates!
  • http://tams-www.informatik.uni-hamburg.de/applets/cmos/index.html
slide4
NAND
  • Not AND - Easier to build than AND – only 4 gates!
  • http://tams-www.informatik.uni-hamburg.de/applets/cmos/index.html
slide5
NOR
  • Not OR
design examples
Design examples
  • Logic circuits provide a solution to a problem
  • Some may be complex and difficult to design
  • Regardless of the complexity, the same basic design issues must be addressed
    • Specify the desired behavior of the circuit
    • Synthesize and implement the circuit
    • Test and verify the circuit
multiplexer circuit
Multiplexer circuit
  • In computer systems it is often necessary to choose data from exactly one of a number of sources
    • Design a circuit that has an output (f) that is exactly the same as one of two data inputs (x,y) based on the value of a control input (s)
      • If s=0 then f=x
      • If s=1 then f=y
    • The function f is really a function of three variables (s,x,y)
    • Describe the function in a three variable truth table
multiplexer circuit1
Multiplexer circuit

f(s,x,y)=m2+m3+m5+m7

f(s,x,y)=s’xy’+s’xy+sx’y+sxy

f(s,x,y)=s’x(y’+y)+sy(x’+x)

f(s,x,y)=s’x+sy

convenient to put

control signal on left

multiplexer circuit2

s

x1

0

1

x2

Multiplexer circuit

f=x1s’+x2s

Graphical symbol

Compact truth table

car safety alarm
Car safety alarm
  • Design a car safety alarm considering four inputs
    • Door closed (D)
    • Key in (K)
    • Seat pressure (S)
    • Seat belt closed (B)
  • The alarm (A) should sound if
    • The key is in and the door is not closed, or
    • The door is closed and the key is in and the driver is in the seat and the seat belt is not closed
car safety alarm1
Car safety alarm

A(D,K,S,B)=Sm(4,5,6,7,14)

A(D,K,S,B)=D’KS’B’+D’KS’B+D’KSB’+D’KSB+DKSB’

=D’KS’+D’KS+KSB’

=D’K+KSB’

xor three way light control
XOR - Three-way light control
  • Assume a room has three doors and a switch by each door controls a single light in the room.
    • Let x, y, and z denote the state of the switches
    • Assume the light is off if all switches are open
    • Closing any switch turns the light on. Closing another switch will have to turn the light off.
    • Light is on if any one switch is closed and off if two (or no) switches are closed.
    • Light is on if all three switches are closed

Lecture 4: Other Logic Gates

three way light control
Three-way light control

f(x,y,z)=m1+m2+m4+m7

f(x,y,z)=x’y’z+x’yz’+xy’z’+xyz

This is the simplest sum-of-products form.

exclusive or xor
The Boolean function OR is more correctly called the Inclusive-OR

The Exclusive-Or, abbreviated XOR with the symbol , operates in the following manner:

X  Y is true if X is true exclusively or if Y is true exclusively but is false if both X and Y are true

X  Y = X’Y + XY’

Exclusive-OR (XOR)
xnor equivalence
The inverse to XOR is XNOR.

XNOR is sometimes listed as the Equivalence function (X  Y)

XNOR/Equivalence is true if both inputs are false or if both inputs are true

X  Y = (XY)’ = X’Y’ + XY

XNOR (Equivalence)
xor and xnor circuit symbols
XOR and XNOR circuit symbols
  • The XOR symbol is similar to the OR symbol with the addition of the additional input bar.
  • The XNOR symbol is equivalent to the XOR symbol with the addition of the inversion circle at the output.

XOR

XNOR

Lecture 4: Other Logic Gates

adder circuit
Adder circuit
  • Design a circuit that adds two input bits together (x,y) and produces two output bits (s and c)
    • S: sum bit
      • x=0, y=0 => s=0
      • x=0, y=1 => s=1
      • x=1, y=0 => s=1
      • x=1, y=1 => s=0
    • C: carry bit
      • x=0, y=0 => c=0
      • x=0, y=1 => c=0
      • x=1, y=0 => c=0
      • x=1, y=1 => c=1
adder circuit1
C = XY

S = X’Y + XY’ = X  Y

Adder Circuit
majority circuit
Majority circuit
  • Design a circuit with three inputs (x,y,z) whose output (f) is 1 only if a majority of the inputs are 1
    • Construct a truth table
    • Write a standard sum-of-products expression for f
    • Draw a circuit diagram for the sum-of-products expression
    • Minimize the function using algebraic manipulation
      • During your minimization you can use any Boolean theorem, but leave the result in sum-of-products form (generate a minimum sum-of-products expression)
    • Draw the minimized circuit
majority function
Majority Function
  • The output of the majority function is equal to the value for the three inputs which occurs on more inputs.
  • Majority(X,Y,Z) = m(3,5,6,7)
  • Majority(X,Y,Z) = X’YZ + XY’Z + XYZ’ + XYZ
  • Simplified  Majority(X,Y,Z) = XY + XZ + YZ
ad