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Advanced ITC Presentation

Advanced ITC Presentation. A. Pogiel J. Rajski J. Tyszer. Motivation. Reliable test response compactor. volume reduction higher than scan chains / channels ratio high observability of scan cells for wide range of X-profiles design simplicity minimum control information. Outline.

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Advanced ITC Presentation

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  1. Advanced ITC Presentation A. PogielJ. Rajski J. Tyszer

  2. Motivation Reliable test response compactor • volume reduction higher than scan chains / channels ratio • high observability of scan cells for wide range of X-profiles • design simplicity • minimum control information

  3. Outline • EDT environment • Compactor architecture • Unknown states • Scan chain selection • Experimental results • Fault diagnosis • Conclusions

  4. Compactedresponses Compressedpatterns EDT architecture • Scan • Deterministic patterns • Embedded test • Selective compaction • Direct diagnosis X-control ATE ATE

  5. 5 4 3 2 1 0 1 2 3 4 5 6 7 8 9 10 11 0 Linear selector

  6. Synthesis algorithm • Generate randomly a polynomial • Verify sharing of mask bits • Determine rank • Repeat 1÷3 for several polynomials • Accept poly with the highest rank • Repeat 1÷5 for all outputs

  7. Linear independence 32 mask bits specified bits New DAC 2001

  8. 64 128 192 256 Encoding efficiency Scan chains: mask bits

  9. Diagnostic resolution Overdrive: 8 1000 single stuck-at faults selected randomly The smallest mask register

  10. Conclusions • Compression higher than scan chains / channels ratio • Programmable scan selector • High observability of scan errors • Immune to high X-fill rates • Proven on industrial designs

  11. Dariusz Czysz, Janusz Rajski, Jerzy Tyszer Second Example Advanced ITC Presentation

  12. purpose Low power scheme compatible with test compression reduced switching during all scan operations preserved test quality accelerated scan shifting

  13. outline • EDT environment • Low power test architecture • Scan shift-in operations • Power aware decompressor • Capture and scan shift-out • Experimental results • Conclusions

  14. motivation 100 scan chains 0.9M gates 45K scan cells Test patterns Scan chains observing faults

  15. control data encoding 0 1 • Constants provided on a per pattern basis • Asserting all variables turn off low power test c1 + c3 + c7 = 0 c2 + c4 + c7 = 1 c3 + c5 + c6 = 0  cn cn-1 … c2 c1 c0

  16. clock gater control data Specified bits refer to bits provided by scan to shut off flip-flops

  17. Load Unload Capture experimental results – filling chains WTM [%] WSA [%] D1 D2 D3 D4 Constant Shadow register Combined

  18. filling chains & clock gating Reduction [%] D1 D2 D3 D4 Load Unload Capture Capture – only clock gaters

  19. conclusions • EDT can deliver low power tests • No impact on quality • Significant reduction of test power in shift • Flexible trade-offs • power efficiency • compression • test application time

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