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Lecture 10b I/O Introduction: Storage Devices, Metrics, & Productivity. Pradondet Nilagupta Original note from Professor David A. Patterson Spring 2001. Storage System Issues. Historical Context of Storage I/O Secondary and Tertiary Storage Devices Storage I/O Performance Measures

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Lecture 10b i o introduction storage devices metrics productivity

Lecture 10b I/O Introduction: Storage Devices, Metrics, & Productivity

Pradondet Nilagupta

Original note from

Professor David A. Patterson

Spring 2001


Storage system issues
Storage System Issues

  • Historical Context of Storage I/O

  • Secondary and Tertiary Storage Devices

  • Storage I/O Performance Measures

  • Processor Interface Issues

  • A Little Queuing Theory

  • Redundant Arrarys of Inexpensive Disks (RAID)

  • I/O Buses


A communication centric world
A Communication-Centric World

  • Computation is getting distributed …

    • Internet, WAN, LAN, BodyLAN, Home Networks, Microprocessor Peripherals, Processor-Memory Interface, System-on-a-Chip

  • Efficient Networking and Communication is Crucial

  • The System-on-a-Chip implies the Network-on-a-Chip

  • In Next Set of Lectures:

    • Busses and Networks

    • But more importantly, the impact of integration


What is a bus

Processor

Input

Control

Memory

Datapath

Output

What is a bus?

A Bus Is:

  • shared communication link

  • single set of wires used to connect multiple subsystems

  • A Bus is also a fundamental tool for composing large, complex systems

    • systematic means of abstraction



Advantages of buses

Memory

Processer

Advantages of Buses

  • Versatility:

    • New devices can be added easily

    • Peripherals can be moved between computersystems that use the same bus standard

  • Low Cost:

    • A single set of wires is shared in multiple ways

I/O Device

I/O Device

I/O Device


Disadvantage of buses

Memory

Processor

Disadvantage of Buses

  • It creates a communication bottleneck

    • The bandwidth of that bus can limit the maximum I/O throughput

  • The maximum bus speed is largely limited by:

    • The length of the bus

    • The number of devices on the bus

    • The need to support a range of devices with:

      • Widely varying latencies

      • Widely varying data transfer rates

I/O Device

I/O Device

I/O Device


General organization of a bus
General Organization of a Bus

Control Lines

Data Lines

  • Control lines:

    • Signal requests and acknowledgments

    • Indicate what type of information is on the data lines

  • Data lines carry information between the source and the destination:

    • Data and Addresses

    • Complex commands


Master versus slave
Master versus Slave

Master issues command

Bus

Master

Bus

Slave

Data can go either way

  • A bus transaction includes two parts:

    • Issuing the command (and address) – request

    • Transferring the data – action

  • Master is the one who starts the bus transaction by:

    • issuing the command (and address)

  • Slave is the one who responds to the address by:

    • Sending data to the master if the master ask for data

    • Receiving data from the master if the master wants to send data


Types of busses
Types of Busses

  • Processor-Memory Bus (design specific)

    • Short and high speed

    • Only need to match the memory system

      • Maximize memory-to-processor bandwidth

    • Connects directly to the processor

    • Optimized for cache block transfers

  • I/O Bus (industry standard)

    • Usually is lengthy and slower

    • Need to match a wide range of I/O devices

    • Connects to the processor-memory bus or backplane bus

  • Backplane Bus (standard or proprietary)

    • Backplane: an interconnection structure within the chassis

    • Allow processors, memory, and I/O devices to coexist

    • Cost advantage: one bus for all components


Example pentium system organization
Example: Pentium System Organization

Processor/Memory

Bus

PCI Bus

I/O Busses


A computer system with one bus backplane bus
A Computer System with One Bus: Backplane Bus

Backplane Bus

Processor

Memory

  • A single bus (the backplane bus) is used for:

    • Processor to memory communication

    • Communication between I/O devices and memory

  • Advantages: Simple and low cost

  • Disadvantages: slow and the bus can become a major bottleneck

  • Example: IBM PC - AT

I/O Devices


A two bus system

Processor Memory Bus

Processor

Memory

Bus

Adaptor

Bus

Adaptor

Bus

Adaptor

I/O

Bus

I/O

Bus

I/O

Bus

A Two-Bus System

  • I/O buses tap into the processor-memory bus via bus adaptors:

    • Processor-memory bus: mainly for processor-memory traffic

    • I/O buses: provide expansion slots for I/O devices

  • Apple Macintosh-II

    • NuBus: Processor, memory, and a few selected I/O devices

    • SCCI Bus: the rest of the I/O devices


A three bus system

Processor Memory Bus

Processor

Memory

Bus

Adaptor

Bus

Adaptor

I/O Bus

Backplane Bus

Bus

Adaptor

I/O Bus

A Three-Bus System

  • A small number of backplane buses tap into the processor-memory bus

    • Processor-memory bus is only used for processor-memory traffic

    • I/O buses are connected to the backplane bus

  • Advantage: loading on the processor bus is greatly reduced


North south bridge architectures separate busses

Processor

Memory

North/South Bridge architectures: separate busses

Processor Memory Bus

“backside

cache”

  • Separate sets of pins for different functions

    • Memory bus

    • Caches

    • Graphics bus (for fast frame buffer)

    • I/O busses are connected to the backplane bus

  • Advantage:

    • Busses can run at different speeds

    • Much less overall loading!

Bus

Adaptor

I/O Bus

Backplane Bus

Bus

Adaptor

I/O Bus


What defines a bus
What defines a bus?

Transaction Protocol

Timing and Signaling Specification

Bunch of Wires

Electrical Specification

Physical / Mechanical Characteristics

– the connectors


Synchronous and asynchronous bus
Synchronous and Asynchronous Bus

  • Synchronous Bus:

    • Includes a clock in the control lines

    • A fixed protocol for communication that is relative to the clock

    • Advantage: involves very little logic and can run very fast

    • Disadvantages:

      • Every device on the bus must run at the same clock rate

      • To avoid clock skew, they cannot be long if they are fast

  • Asynchronous Bus:

    • It is not clocked

    • It can accommodate a wide range of devices

    • It can be lengthened without worrying about clock skew

    • It requires a handshaking protocol


Busses so far
Busses so far

Master

Slave

° ° °

Control Lines

Bus Master: has ability to control the bus, initiates transaction

Bus Slave: module activated by the transaction

Bus Communication Protocol: specification of sequence of events and timing requirements in transferring information.

Asynchronous Bus Transfers: control lines (req, ack) serve to orchestrate sequencing.

Synchronous Bus Transfers: sequence relative to common clock.

Address Lines

Data Lines


Bus transaction
Bus Transaction

  • Arbitration: Who gets the bus

  • Request: What do we want to do

  • Action: What happens in response


Arbitration obtaining access to the bus
Arbitration: Obtaining Access to the Bus

Control: Master initiates requests

Bus

Master

Bus

Slave

Data can go either way

  • One of the most important issues in bus design:

    • How is the bus reserved by a device that wishes to use it?

  • Chaos is avoided by a master-slave arrangement:

    • Only the bus master can control access to the bus:

      It initiates and controls all bus requests

    • A slave responds to read and write requests

  • The simplest system:

    • Processor is the only bus master

    • All bus requests must be controlled by the processor

    • Major drawback: the processor is involved in every transaction


Multiple potential bus masters the need for arbitration
Multiple Potential Bus Masters: the Need for Arbitration

  • Bus arbitration scheme:

    • A bus master wanting to use the bus asserts the bus request

    • A bus master cannot use the bus until its request is granted

    • A bus master must signal to the arbiter the end of the bus utilization

  • Bus arbitration schemes usually try to balance two factors:

    • Bus priority: the highest priority device should be serviced first

    • Fairness: Even the lowest priority device should never be completely locked out from the bus

  • Bus arbitration schemes can be divided into four broad classes:

    • Daisy chain arbitration

    • Centralized, parallel arbitration

    • Distributed arbitration by self-selection: each device wanting the bus places a code indicating its identity on the bus.

    • Distributed arbitration by collision detection: Each device just “goes for it”. Problems found after the fact.


The daisy chain bus arbitrations scheme
The Daisy Chain Bus Arbitrations Scheme

Device 1

Highest

Priority

Device N

Lowest

Priority

Device 2

  • Advantage: simple

  • Disadvantages:

    • Cannot assure fairness: A low-priority device may be locked out indefinitely

    • The use of the daisy chain grant signal also limits the bus speed

Grant

Grant

Grant

Release

Bus

Arbiter

Request

wired-OR


Centralized parallel arbitration
Centralized Parallel Arbitration

Device 1

Device N

Device 2

  • Used in essentially all processor-memory busses and in high-speed I/O busses

Req

Grant

Bus

Arbiter


Simplest bus paradigm
Simplest bus paradigm

  • All agents operate synchronously

  • All can source / sink data at same rate

  • => simple protocol

    • just manage the source and target


Simple synchronous protocol
Simple Synchronous Protocol

BReq

  • Even memory busses are more complex than this

    • memory (slave) may take time to respond

    • it may need to control data rate

BG

R/W

Address

Cmd+Addr

Data1

Data2

Data


Typical synchronous protocol
Typical Synchronous Protocol

BReq

  • Slave indicates when it is prepared for data xfer

  • Actual transfer goes at bus rate

BG

R/W

Address

Cmd+Addr

Wait

Data1

Data1

Data2

Data


Increasing the bus bandwidth
Increasing the Bus Bandwidth

  • Separate versus multiplexed address and data lines:

    • Address and data can be transmitted in one bus cycleif separate address and data lines are available

    • Cost: (a) more bus lines, (b) increased complexity

  • Data bus width:

    • By increasing the width of the data bus, transfers of multiple words require fewer bus cycles

    • Example: SPARCstation 20’s memory bus is 128 bit wide

    • Cost: more bus lines

  • Block transfers:

    • Allow the bus to transfer multiple words in back-to-back bus cycles

    • Only one address needs to be sent at the beginning

    • The bus is not released until the last word is transferred

    • Cost: (a) increased complexity (b) decreased response time for request


Increasing transaction rate on multimaster bus
Increasing Transaction Rate on Multimaster Bus

  • Overlapped arbitration

    • perform arbitration for next transaction during current transaction

  • Bus parking

    • master holds onto bus and performs multiple transactions as long as no other master makes request

  • Overlapped address / data phases

    • requires one of the above techniques

  • Split-phase (or packet switched) bus

    • completely separate address and data phases

    • arbitrate separately for each

    • address phase yield a tag which is matched with data phase

  • ”All of the above” in most modern memory buses


1993 cpu memory bus survey
1993 CPU- Memory Bus Survey

Bus MBus Summit Challenge XDBus

Originator Sun HP SGI Sun

Clock Rate (MHz) 40 60 48 66

Address lines 36 48 40 muxed

Data lines 64 128 256 144 (parity)

Data Sizes (bits) 256 512 1024 512

Clocks/transfer 4 5 4?

Peak (MB/s) 320(80) 960 1200 1056

Master Multi Multi Multi Multi

Arbitration Central Central Central Central

Slots 16 9 10

Busses/system 1 1 1 2

Length 13 inches 12? inches 17 inches


Asynchronous handshake 4 phase
Asynchronous Handshake (4-phase)

Write Transaction

Address

Data

Read

Req

Ack

Master Asserts Address

Next Address

Master Asserts Data

  • t0 : Master has obtained control and asserts address, direction, data

  • Waits a specified amount of time for slaves to decode target

  • t1: Master asserts request line

  • t2: Slave asserts ack, indicating data received

  • t3: Master releases req

  • t4: Slave releases ack

t0 t1 t2 t3 t4 t5


Read transaction
Read Transaction

Address

Data

Read

Req

Ack

Master Asserts Address

Next Address

Slave Data

  • t0 : Master has obtained control and asserts address, direction, data

  • Waits a specified amount of time for slaves to decode target\

  • t1: Master asserts request line

  • t2: Slave asserts ack, indicating ready to transmit data

  • t3: Master releases req, data received

  • t4: Slave releases ack

t0 t1 t2 t3 t4 t5


1993 backplane io bus survey
1993 Backplane/IO Bus Survey

Bus SBus TurboChannel MicroChannel PCI

Originator Sun DEC IBM Intel

Clock Rate (MHz) 16-25 12.5-25 async 33

Addressing Virtual Physical Physical Physical

Data Sizes (bits) 8,16,32 8,16,24,32 8,16,24,32,64 8,16,24,32,64

Master Multi Single Multi Multi

Arbitration Central Central Central Central

32 bit read (MB/s) 33 25 20 33

Peak (MB/s) 89 84 75 111 (222)

Max Power (W) 16 26 13 25


High speed i o bus
High Speed I/O Bus

  • Examples

    • graphics

    • fast networks

  • Limited number of devices

  • Data transfer bursts at full rate

  • DMA transfers important

    • small controller spools stream of bytes to or from memory

  • Either side may need to squelch transfer

    • buffers fill up


Pci read write transactions
PCI Read/Write Transactions

  • All signals sampled on rising edge

  • Centralized Parallel Arbitration

    • overlapped with previous transaction

  • All transfers are (unlimited) bursts

  • Address phase starts by asserting FRAME#

  • Next cycle “initiator” asserts cmd and address

  • Data transfers happen on when

    • IRDY# asserted by master when ready to transfer data

    • TRDY# asserted by target when ready to transfer data

    • transfer when both asserted on rising edge

  • FRAME# deasserted when master intends to complete only one more data transfer


Pci read transaction
PCI Read Transaction

– Turn-around cycle on any signal driven by more than one agent



The system on a chip nightmare

System Bus

DMA

CPU

DSP

Mem

Ctrl.

Bridge

MPEG

C

I

O

O

Custom Interfaces

Peripheral

Bus

Control Wires

The System-on-a-Chip Nightmare

The “Board-on-a-Chip”

Approach


Sonics soc integration architecture

DMA

DSP

CPU

MPEG

C

MEM

I

O

Sonics SOC Integration Architecture

Open Core Protocol™

{

MultiChip

Backplane™

SiliconBackplane™

(patented)

SiliconBackplane

Agent™


Open core protocol goals
Open Core Protocol Goals

  • Bus Independent

  • Scalable

  • Configurable

  • Synthesis/Timing Analysis Friendly

  • Encompass entire core/system interface needs (data, control, and test flows)


Data control and test flows
Data, Control, and Test Flows

  • Data Flow

    • Signals and protocols associated with moving data

    • Includes address, data, handshaking, etc.

    • Similar to services provided by traditional computer buses

  • Control Flow

    • Signals and protocols associated with non-data communication

    • Sideband - not synchronized to data flow (out of band)

    • Examples include interrupts, high-level flow control, etc.

  • Test Flow

    • Signals and protocols related to debug and manufacturing test


Ocp overview
OCP Overview

  • Point-to-point, uni-directional, synchronous

    • easy physical implementation

  • Master/Slave, request/response

    • well-defined, simple roles

  • Extensions

    • added functionality to support cores with more complex interface requirements

  • Configurability

    • pay only for the features needed for a given core


Master vs slave

IP Core

IP Core

IP Core

Master

Master

Master

Master

Open Core

Protocol

Response

Request

Initiator

Target

On-Chip Bus

Slave

Slave

Slave

Slave

Master vs. Slave


Basic ocp

MCmd, MAddr

SCmdAccept

SResp, SData

SCmdAccept

Clk

MCmd, Maddr, MData

SCmdAccept

Basic OCP

Master

Slave

MCmd [3]

MAddr [N]

MData [N]

SResp [3]

SData [N]

Read:Command, AddressCommand AcceptResponse, Data

Write (posted):Command, Address, DataCommand Accept


Protocol phases
Protocol Phases

  • Request Phase (begins Transfer)

    • Master presents request (command, address, etc.) to Slave

  • Response Phase (ends Transfer)

    • Slave presents response (success/fail, read data) to Master

    • Only available for read transfers (posted write model)

  • Datahandshake Phase (Optional)

    • Allows pipelining request ahead of write data

    • Only available for write transfers

  • Phase ordering

    • Request -> Datahandshake -> Response


Ocp extensions
OCP Extensions

  • Simple Extensions

    • Byte Enables

    • Bursts

    • Flow Control

    • Data Handshake

  • Complex Extensions

    • Threads and Connections

  • Sideband Signals


The backplane why not use a computer bus

Transmit FIFO

Receive FIFO

IP

Core

IP

Core

Arbiter

Address

Computer

Bus

  

Data

  

IP

Core

IP

Core

Time

The Backplane: Why Not Use a Computer Bus?

  • Expensive to decouple

  • Not designed for real-time


Communication buses decouple and guarantee real time

Transmit FIFO

Receive FIFO

IP

Core

IP

Core

TDMA

TDMA

Communications

Bus

  

Data

  

IP

Core

IP

Core

Time

Communication Buses Decouple and Guarantee Real Time

  • Connections are expensive

  • Poor read latency


Siliconbackplane employs best of both

DMA

DSP

CPU

MPEG

C

MEM

I

O

SiliconBackplane™Employs Best of Both

  • From Computing

  • Address-based selection

  • Write and read transfers

  • Pipelining

  • From Communications

  • Efficient BW decoupling

  • Guaranteed BW & latency

  • Side-band signaling


Guaranteed bandwidth arbitration

Arbitration

Command

Guaranteed Bandwidth Arbitration

  • Independent arbitration for every cycle includes two phases:

    • Distributed TDMA

    • Round robin

  • Provides fine control over system bandwidth

Current

Slot


Guaranteed latency
Guaranteed Latency

  • Fixed latency between command/address and data/response phases

  • Matches pipelined CPU model ensuringhigh performance access to on-chip resources

  • Pipelined data routed through SiliconBackplane™

  • Latency re-programmable in software

  • Variable-latency blocks do not tie up the SiliconBackplane


Integrated signaling mechanism
Integrated Signaling Mechanism

  • Dedicated SiliconBackplane™ wires (Flags) support:

    • Bus-style out-of-band signaling (interrupts)

    • Point-to-point communications (flow control)

    • Dynamic point-to-point (retry mechanism)

  • Same design flow, timing, flexibility as address/data portion of SonicsIA™


Multichip backplane extends sonicsia between chips
MultiChip Backplane™ ExtendsSonicsIA™ Between Chips

SiliconBackplane

CPU-Based ASSP

MultiChip Backplane

FPGA

ASSP

Seamless integration of protocols


Validation test

SiliconBackplane™ highly visible for test

All subsystems communicate through SiliconBackplane

Test Interfaces:

MultiChip Backplane: 100’s MB/sec.

ServiceAgent: Scan-based

Each subsystem can be tested/validated stand-alone

Test

Vectors

Test

Vectors

Validation / Test

MultiChip

Backplane™


Summary
Summary

  • Busses are an important technique for building large-scale systems

    • Their speed is critically dependent on factors such as length, number of devices, etc.

    • Critically limited by capacitance

    • Tricks: esoteric drive technology such as GTL

  • Important terminology:

    • Master: The device that can initiate new transactions

    • Slaves: Devices that respond to the master

  • Two types of bus timing:

    • Synchronous: bus includes clock

    • Asynchronous: no clock, just REQ/ACK strobing

  • System-on-a-Chip approach invites new solutions

    • Well-defined and clear communication protocols

    • Physical layer hidden to designer


Interconnect trends
Interconnect Trends

  • Interconnect = glue that interfaces computer system components

  • High speed hardware interfaces + logical protocols

  • Networks, channels, backplanes

memory-mapped

wide pathways

centralized arb

message-based

narrow pathways

distributed arb


Backplane architectures
Backplane Architectures

Distinctions begin to blur:

SCSI channel is like a bus

FutureBus is like a channel (disconnect/reconnect)

HIPPI forms links in high speed switching fabrics


Bus based interconnect
Bus-Based Interconnect

  • Bus: a shared communication link between subsystems

    • Low cost: a single set of wires is shared multiple ways

    • Versatility: Easy to add new devices & peripherals may even be ported between computers using common bus

  • Disadvantage

    • A communication bottleneck, possibly limiting the maximum I/O throughput

  • Bus speed is limited by physical factors

    • the bus length

    • the number of devices (and, hence, bus loading).

    • these physical limits prevent arbitrary bus speedup.


Bus based interconnect1
Bus-Based Interconnect

  • Two generic types of busses:

    • I/O busses: lengthy, many types of devices connected, wide range in the data bandwidth), and follow a bus standard(sometimes called a channel)

    • CPU–memory buses: high speed, matched to the memory system to maximize memory–CPU bandwidth, single device (sometimes called a backplane)

    • To lower costs, low cost (older) systems combine together

  • Bus transaction

    • Sending address & receiving or sending data


Bus protocols
Bus Protocols

Master

Slave

ฐ ฐ ฐ

Control Lines

Bus Master: has ability to control the bus, initiates transaction

Bus Slave: module activated by the transaction

Bus Communication Protocol: specification of sequence of events and timing requirements in transferring information.

Asynchronous Bus Transfers: control lines (req., ack.) serve to orchestrate sequencing

Synchronous Bus Transfers: sequence relative to common clock

Address Lines

Data Lines

Multibus: 20 address, 16 data, 5 control, 50ns Pause


Synchronous bus protocols
Synchronous Bus Protocols

Clock

Address

Data

Read

Wait

Read complete

begin read

Pipelined/Split transaction Bus Protocol

Address

Data

Wait

addr 1

addr 2

addr 3

data 0

data 1

data 2

wait 1

OK 1


Asynchronous handshake
Asynchronous Handshake

Write Transaction

Address

Data

Read

Req.

Ack.

Master Asserts Address

Next Address

t0 : Master has obtained control and asserts address, direction, data

Waits a specified amount of time for slaves to decode target\

t1: Master asserts request line

t2: Slave asserts ack, indicating data received

t3: Master releases req

t4: Slave releases ack

Master Asserts Data

4 Cycle Handshake

t0 t1 t2 t3 t4 t5


Read transaction1
Read Transaction

Address

Data

Read

Req

Ack

Master Asserts Address

Next Address

t0 : Master has obtained control and asserts address, direction, data

Waits a specified amount of time for slaves to decode target\

t1: Master asserts request line

t2: Slave asserts ack, indicating ready to transmit data

t3: Master releases req, data received

t4: Slave releases ack

4 Cycle Handshake

t0 t1 t2 t3 t4 t5

Time Multiplexed Bus: address and data share lines


Bus arbitration
Bus Arbitration

Parallel (Centralized) Arbitration

Serial Arbitration (daisy chaining)

Polling

Bus Request

Bus Grant

BR BG

BR BG

BR BG

M

M

M

BG

BR

BGi BGo

BGi BGo

BGi BGo

M

M

M

A.U.

BR

BR

BR

M

M

M

A.U.

BR A C

BR A C

BR A C

BR

A


Bus options
Bus Options

Option High performance Low cost

Bus width Separate address Multiplex address & data lines & data lines

Data width Wider is faster Narrower is cheaper (e.g., 32 bits) (e.g., 8 bits)

Transfer size Multiple words has Single-word transfer less bus overhead is simpler

Bus masters Multiple Single master (requires arbitration) (no arbitration)

Split Yes—separate No—continuous transaction? Request and Reply connection is cheaper packets gets higher and has lower latency bandwidth (needs multiple masters)

Clocking Synchronous Asynchronous


1990 bus survey p h 1st ed
1990 Bus Survey (P&H, 1st Ed)

VME FutureBus Multibus II IPI SCSI

Signals 128 96 96 16 8

Addr/Data mux no yes yes n/a n/a

Data width 16 - 32 32 32 16 8

Masters multi multi multi single multi

Clocking Async Async Sync Async either

MB/s (0ns, word) 25 37 20 25 1.5 (asyn)

5 (sync)

150ns word 12.9 15.5 10 = =

0ns block 27.9 95.2 40 = =

150ns block 13.6 20.8 13.3 = =

Max devices 21 20 21 8 7

Max meters 0.5 0.5 0.5 50 25

Standard IEEE 1014 IEEE 896.1 ANSI/IEEE ANSI X3.129 ANSI X3.131

1296


VME

  • 3 96-pin connectors

  • 128 defined as standard, rest customer defined

    • 32 address

    • 32 data

    • 64 command & power/ground lines


Scsi small computer system interface
SCSI: Small Computer System Interface

  • Clock rate: 5 MHz / 10 MHz (fast) / 20 MHz (ultra)

  • Width: n = 8 bits / 16 bits (wide); up to n – 1 devices to communicate on a bus or “string”

  • Devices can be slave (“target”) or master(“initiator”)

  • SCSI protocol: a series of “phases”, during which specif-ic actions are taken by the controller and the SCSI disks

    • Bus Free: No device is currently accessing the bus

    • Arbitration: When the SCSI bus goes free, multiple devices may request (arbitrate for) the bus; fixed priority by address

    • Selection: informs the target that it will participate (Reselection if disconnected)

    • Command: the initiator reads the SCSI command bytes from host memory and sends them to the target

    • Data Transfer: data in or out, initiator: target

    • Message Phase: message in or out, initiator: target (identify, save/restore data pointer, disconnect, command complete)

    • Status Phase: target, just before command complete


Scsi bus channel architecture
SCSI “Bus”: Channel Architecture

peer-to-peer protocols

initiator/target

linear byte streams

disconnect/reconnect


1993 i o bus survey p h 2nd ed
1993 I/O Bus Survey (P&H, 2nd Ed)

Bus SBus TurboChannel MicroChannel PCI

Originator Sun DEC IBM Intel

Clock Rate (MHz) 16-25 12.5-25 async 33

Addressing Virtual Physical Physical Physical

Data Sizes (bits) 8,16,32 8,16,24,32 8,16,24,32,64 8,16,24,32,64

Master Multi Single Multi Multi

Arbitration Central Central Central Central

32 bit read (MB/s) 33 25 20 33

Peak (MB/s) 89 84 75 111 (222)

Max Power (W) 16 26 13 25


1993 mp server memory bus survey
1993 MP Server Memory Bus Survey

Bus Summit Challenge XDBus

Originator HP SGI Sun

Clock Rate (MHz) 60 48 66

Split transaction?YesYes Yes?

Address lines 48 40 ??

Data lines 128 256 144 (parity)

Data Sizes (bits) 512 1024 512

Clocks/transfer 4 5 4?

Peak (MB/s) 960 1200 1056

Master Multi Multi Multi

Arbitration Central Central Central

Addressing Physical Physical Physical

Slots 16 9 10

Busses/system 1 1 2

Length 13 inches 12? inches 17 inches


Communications networks
Communications Networks

Performance limiter is memory system, OS overhead

  • Send/receive queues in processor memories

  • Network controller copies back and forth via DMA

  • No host intervention needed

  • Interrupt host when message sent or received


I o controller architecture
I/O Controller Architecture

Request/response block interface

Backdoor access to host memory


I o data flow
I/O Data Flow

Impediment to high performance: multiple copies,

complex hierarchy


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