2005 Spring Deliverables

1. Design and System Driver ChaptersSpring Meeting April 2005Munich, GermanyDesign TWG (Europe, Asia, and U.S.) Albin, Arledge, Asada,Bernstein, Bertacco, Blaauw, Blanton,Brederlow,Briere,Carballo, Chen,Cohn,Cottrell,Darringer,Edwards,Furui,Gowda, Guardiani, Hiwatashi, Kahng, kashiwagi,Kawahira,Kozawa,Ishibashi,Kravets, Martin, McMillan, Nassif, Pan, Macd, Nukiyama, Pitchumani, Pixley,Rosenstiel, Read, Rodgers, Sakallah, Smith,Soma,Stok,Vertregt,Wilson, Yamamoto, Yamada, Yeh

2. 2005 Spring Deliverables • 10 new table drafts quantify design technology trends • Final version targeted by June • DFM preliminary model enables variability roadmap • DFM roadmapping tool + interface with other groups • Draft SoC cost model provides new type of driver • SoC model quantifies productivity and architecture trends

3. Timeline

4. Design: Content organization • Promotion of key design challenges • Small subset of them to top-level ORTC General Selection Productivity Power DFM Interference Reliability Mapping Design process System design Logic/circuit Physical D Design verification Design Test DFM (new)

5. Design: Content organization (II) Scope Complexity and Crosscutting Challenges Design Technology Challenges - Overall Challenges (5 challenges + table) - Design Methodology Trends (text) - System-level Design - Logical, Circuit, and Physical Design - AMS and RF-specific DT Trends and Challenges (revised) - Design Verification - Design Test

6. Detailed Table Status • Targeting 50-60 new rows • Leads: Rosenstiel, Soma, Bertacco, Kravets, Nassif/Kahng • Next steps • Incorporate input until final version • Complete coloring

7. New Table: System-Level Requirements Source: Wolfgang Rosenstiel’s Team

8. New Table: System-Level Solutions 2006 2009 2012 2015 2018 2005 2011 2013 2014 2017 2010 2016 2019 2020 2007 2008 Technology Node hp70 hp50 hp35 hp25 hp18 hp15 System-level component reuse Chip-package co-design methods Explicit system-level energy-performance trade-off On-chip network design methods Automated Interface Synthesis SW-SW and SW-HW co-design and verification Multi-fabric implementation planning (AMS, RF, MEMS, …) Improvement Pre-Production Research Required Development Time during which research, development, and qualification/pre-production should be taking place for solution. 2021 Source: Wolfgang Rosenstiel’s Team

9. New Table: Logic/Ckt/Physical Requirements Source: Victor Kravets’s Team

10. New Table: Logic/Ckt/Physical Requirements Source: Victor Kravets’s Team

11. New Table: Verification Requirements • Bugs • escape rate: bugs found after first tape out. • bugs found after system integration until tape-out Code coverage • percent of code coverage Functional coverage • percent of the projects where it is used • functional coverage goals for each thousand lines of HDL code • correlation of size of functional coverage goal vs. escape rate Tape-out criteria • examples: booting linux, total number of simulation cycle run, coverage.... Reuse • ratio of fresh verification infrastructure vs. reused • percent of reused infrastructure that is acquired from third parties Methodology • effort spent in formal verification vs. simulation/emulation (in engineering days) • effort spent in formal verification vs. simulation/emulation (in lines of HDL) • Verification requirements Source: Valeria Bertacco’s Team

12. New Table: DFT Requirements Source: Mani Soma’sTeam

14. New Table: DFM Requirements Source: Carballo/Nassif/Pan/Kahng/Guardiani/Brederlow/Wong

15. New Table: DFM Solutions Source: Carballo/Nassif/Pan/Kahng/Guardiani/Brederlow/Wong

16. 2. SoC Cost Model Update, Inc. SW ES Level Methodology Very large block reuse Intelligent testbench Large block reuse Small block reuse Tall thin engineer IC implem. tools In-house P&R General $10,000 $1,000 Selection Productivity Power Manufac. Interference Reliability $100 Design cost ($M) $10 $1 Design process System design Logic/circuit Physical D Design verification Design Test DFM (new) 1990 1996 2000 2002 2004 2010 1992 1994 1998 2006 2008 Mobile /Consumer SoC PE-1 PE-2 … PE-n Main Prc. Memory Updated productivity table  cost Peripherals Will preserve consistency

17. # of Processing Engines

18. Processing Power Trends

19. HW Design Productivity Requirements

20. 3. New DFM Section –Outline • INTRO • DFM CHALLENGES -- NEAR TERM (>45 NM) • MASK COST • DATA EXPLOSION • LIMITATIONS OF LITHOGRAPHY HARDWARE RESOLUTION • VOLTAGE SUPPLY AND THRESHOLD VARIABILITY • BEOL PLANARIZATION AND DIMENSIONAL VARIABILITY • HETEROGENEOUS COMPONENTS (AMS, MEMS, ERAM) • LEAKAGE AS A LIMITER OF MANUFACTURABILITY • VARIABILITY • DFM CHALLENGES -- LONG TERM (<45 NM) - UNCONTROLLABLE CD AND DOPING VARIABILITY - EXTREME DEVICE AND CIRCUIT VARIABILITY • RET-awareness IN DESIGN • PACKAGE, SYSTEM, AND SW VARIABILITY • BEOL PLANARIZATION AND DIMENSIONAL VARIABILITY • DESCRIPTION OF VARIABILITY MODEL

21. DFM  Variability Framework Actual (bottom-up) / required (top-down) variability Performance (delay) Power (energy) “Gate” delay (power) “Wire” delay (power) Intermediate parameters Intermediate parameters (Vdd, T) Rsheet Vt Leff tOX NA Weff L t W tILD Other TWGs (PIDS, Interconnect, etc.)

22. Roadmapping DFM Issues inc. Variability • Current recommendation • Not to extend 10% CD control beyond 15% • Below 15% still unclear