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Language Overview III. The finish of a grand tour of the language. Elements Covered in III. Reminder from I and II: Language overview lectures do not cover all aspects of the language. But they do cover a large portion of it. Concurrent Statements Sequential Statements Now

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Language overview iii l.jpg

Language Overview III

The finish of a grand tour of the language.

Copyright 2006 - Joanne DeGroat, ECE, OSU


Elements covered in iii l.jpg
Elements Covered in III

  • Reminder from I and II: Language overview lectures do not cover all aspects of the language. But they do cover a large portion of it.

    • Concurrent Statements

    • Sequential Statements

  • Now

    • ENTITIES, ARCHITECTURES, PACKAGES, PROCEDURES AND FUNCTIONS, OVERLOADING, LIBRARIES and the USE clause.

Copyright 2006 - Joanne DeGroat, ECE, OSU


The entity l.jpg
The ENTITY

  • The basic concept of VHDL is that you have and interface and the function of the circuit within that interface.

  • The interface (ENTITY) tells you what data and control arrives and how it arrives.

  • The function (ARCHITECTURE) tells you how you operate on the data to produce results or respond to the inputs.

Copyright 2006 - Joanne DeGroat, ECE, OSU


The entity4 l.jpg
THE ENTITY

  • entity_declaration::=

  • entity identifieris

  • entity_header

  • entity_declarative_part

  • [begin

  • entity_statement_part]

  • end [identifier];

  • entity_header::= [formal_generic_clause]

  • [formal_port_clause]

Copyright 2006 - Joanne DeGroat, ECE, OSU


The entity5 l.jpg
The ENTITY

  • formal_generic_clause::= generic (generic_list);

  • formal_port_clause::= port (port_list);

  • entity_declarative_part::= {entity_declarative_item}

  • entity_declarative_item::=

  • subprogram_declaration

  • | subprogram_body

  • | type_declaration

  • | subtype_declaration

  • | constant_declaration

  • | signal_declaration

  • | file_declaration

  • | alias_declaration

  • | attribute_declaration

  • | attribute_specification

  • | disconnect_specification

  • | use_clause

Items declared

in the ENTITY

have scope over

all architectures

of the entity

Copyright 2006 - Joanne DeGroat, ECE, OSU


The entity6 l.jpg
The ENTITY

  • entity_statement_part::= entity_statement

  • entity_statement::=

  • concurrent_assertion_statement

  • | passive_concurrent_procedure_call

  • | passive_process_statement

  • Passive means that the process or procedure call contains no signal assignment statements, nor calls to any other procedure which contains a signal assignment statement.

  • Thus these passive procedure calls and processes can do monitoring only. They can use assertion statements to report status of the signals they are monitoring.

  • Copyright 2006 - Joanne DeGroat, ECE, OSU


    The entity7 l.jpg
    The ENTITY

    • EXAMPLE

      • entity LATCH is

      • port (DIN: in WORD; DOUT: out WORD;

      • LOAD, CLK : in BIT);

      • constant SETUP : TIME := 12 ns;

      • constant PulseWidth : TIME := 50 ns;

      • use WORK.TimingMonitors.all;

      • begin

      • CheckTiming (SETUP,DIN,LOAD,CLK);

      • end LATCH;

    Copyright 2006 - Joanne DeGroat, ECE, OSU


    The architecture l.jpg
    The Architecture

    • This is the design unit that describes the function of the design

      • Dataflow – using concurrent signal assignments = very, very close to the actual logic – a form of RTL

      • RTL – register transfer level = just above dataflow and similar to RTL for a processor architecture

      • Behavioral – algorithmic description of the functional behavior – very useful for reference models

    Copyright 2006 - Joanne DeGroat, ECE, OSU


    The architecture9 l.jpg
    The Architecture

    • architecture identifierof entity_name is

    • architecture_declarative_part

    • begin

    • architecture_statement_part

    • end [identifier];

    • architecture_declarative_part::=

    • {architecture_declarative_item}

    • architecture_statement_part::= {concurrent_statement}

    Copyright 2006 - Joanne DeGroat, ECE, OSU


    The architecture10 l.jpg
    The Architecture

    • architecture_declarative_item::=

    • subprogram_declaration

    • | subprogram_body

    • | type_declaration

    • | subtype_declaration

    • | constant_declaration

    • | signal_declaration

    • | file_declaration

    • | alias_declaration

    • | component_declaration

    • | attribute_declaration

    • | attribute_specification

    • | configuration_specification

    • | disconnect_specification

    • | use_clause

    Copyright 2006 - Joanne DeGroat, ECE, OSU


    Packages l.jpg
    Packages

    • Packages provide a convenient way to declare commonly used declarations, functions, and procedures and make them available to many entities, architectures, and other packages.

    • Consists of two parts

      • The Package Declaration

      • The Package Body

    Copyright 2006 - Joanne DeGroat, ECE, OSU


    Package declaration l.jpg
    Package Declaration

    • packageidentifieris

    • package_declarative_part

    • end [identifier];

    • package_declarative_part::={package_declarative_item}

    • package_declarative_item::=

    • subprogram_declaration

    • | type_declaration

    • | subtype_declaration

    • | constant_declaration

    • | signal_declaration

    • | file_declaration

    • | alias_declaration

    • | component_declaration

    • | attribute_declaration

    • | attribute_specification

    • | disconnect_specification

    • | use_clause

    Copyright 2006 - Joanne DeGroat, ECE, OSU


    Example of package declaration l.jpg
    Example of Package Declaration

    • package TriState is

    • type TRI is (‘0’,’1’,’Z’,’E’);

    • function BitVal (value:TRI) return BIT;

    • function TriVal (value:BIT) return TRI;

    • end TriState;

    Copyright 2006 - Joanne DeGroat, ECE, OSU


    Slide14 l.jpg

    Copyright 2006 - Joanne DeGroat, ECE, OSU


    Package body l.jpg
    Package Body

    • package body identifieris

    • package_body_declarative_part

    • end [identifier];

    • package_body_declarative_part::=

    • {package_body_declarative_item}

    • package_body_declarative_item::=

    • subprogram_declaration

    • | subprogram_body

    • | type_declaration

    • | subtype_declaration

    • | constant_declaration

    • | file_declaration

    • | alias_declaration

    • | use_clause

    Copyright 2006 - Joanne DeGroat, ECE, OSU


    Example l.jpg
    Example

    • package body TriState is

    • function BitVal (value:TRI) return BIT is

    • constant bits : BIT_VECTOR := (“0100”);

    • begin

    • return bits(TRI’POS(value));

    • end;

    • function TriVal (value:BIT) return Tri is

    • begin

    • return Tri’Val(BIT’POS(value));

    • end;

    Copyright 2006 - Joanne DeGroat, ECE, OSU


    Notes on packages l.jpg
    Notes on Packages

    • Note: Only what is declared in the package declaration is visible outside the package!!!

    • Items declared inside the package body are only visible inside the package body.

    Copyright 2006 - Joanne DeGroat, ECE, OSU


    Functions and procedures l.jpg
    Functions and Procedures

    • Sequential statements are used within Functions and Procedures

    • Declaration

      • procedure designator [(formal_parameter_list)];

      • function designator [(formal_parameter_list)]

      • return type_mark;

    Copyright 2006 - Joanne DeGroat, ECE, OSU


    Functions and procedures19 l.jpg
    Functions and Procedures

    • The Body

      • procedure designator [(formal_parameter_list)] is

      • subprogram_declarative_part

      • begin

      • subprogram_statement_part

      • end [designator];

      • function designator [(formal_parameter_list)] return type_mark is

      • subprogram_declarative_part

      • begin

      • subprogram_statement_part

      • end [designator];

    Copyright 2006 - Joanne DeGroat, ECE, OSU


    Functions and procedures20 l.jpg
    Functions and Procedures

    • Functions must use a return statement as they must return a value

      • function fg1 (w,x,g1 : IN BIT) return BIT;

      • function fg1 (w,x,g1 : IN BIT) return BIT is

      • BEGIN

      • return (w and g1) or (not x and g1) or

      • (w and not x);

      • END;

    Copyright 2006 - Joanne DeGroat, ECE, OSU


    Other item of significance overloading l.jpg
    Other item of significance - OVERLOADING

    • Overloading – You can overload any function or procedure in VHDL.

    • EXAMPLE:

      • procedure WRITE (F: inout TEXT; value:Integer);

      • procedure WRITE (F: inout TEXT; value : String);

      • These are two declarations for an overloaded procedure WRITE

      • (if no mode is given on the arguments to a procedure or function the mode in is presumed)

      • USAGE DETERMINES WHICH VERSION OF THE PROCEDURE WILL BE USED

      • USAGE

        • write (MY_FILE, VAR);

        • WRITE(sys_output, 12); WRITE(sys_error, “Actual output doesn’t match”);

    Copyright 2006 - Joanne DeGroat, ECE, OSU


    Overloaded functions l.jpg
    Overloaded Functions

    • type MVL is (‘0’,’1’,’Z’,’X’);

    • function “and” (L,R : MVL) return MVL;

    • function “or” (L,R : MVL) return MVL;

    • USAGE:

      • signal Q,R,S : MVL

      • Q <= ‘X’ or ‘1’;

      • R <= S and Q;

    Copyright 2006 - Joanne DeGroat, ECE, OSU


    Libraries and use l.jpg
    Libraries and Use

    • Libraries provide a place to organize and store the design units – entities – architectures – package declarations – package bodies – that we have written and analyzed.

    • Then to use those design units we need to make them visible with the current design unit so it can see, and thus use, them.

    Copyright 2006 - Joanne DeGroat, ECE, OSU


    The library clause l.jpg
    The Library clause

    • Allows the use of design units from other libraries.

    • When a library is created it has both an actual name and a logical name. The actual name is the file system name within the file system of the host computer system. The logical name if the name used within the VHDL system.

    • LIBRARIES WORK and STD are visible to all design units.

    Copyright 2006 - Joanne DeGroat, ECE, OSU


    Library clause l.jpg
    Library clause

    • library logical_name_list;

    • logical_name_list::=logical_name{,logical_name}

  • This will make the logical_name(s) visible to the current design unit

  • Declared just before the start of the design unit

    • library WORK, MY_LIB;

    • entity and_gate is

    • PORT (A,B : in BIT; X : out BIT);

    • end and_gate;

  • Copyright 2006 - Joanne DeGroat, ECE, OSU


    Library clause and packages l.jpg
    Library Clause and Packages

    • The library clause only makes the entities visible. It does not make any declarations within the package visible.

    • Need to use a USE clause to make package declarations visible.

    • USE clause:

      • use library_name.package_name.items

    • where items may be specific items or the reserved word all

    Copyright 2006 - Joanne DeGroat, ECE, OSU


    Example of use l.jpg
    Example of USE

    • library ls7400;

    • use ls7400.gates.all;

    • entity new_thing is …..

  • where gates is a package with library ls7400.

  • The all makes all declarations in package gates visible.

  • ALL DESIGN UNITS ARE CONSIDERED TO HAVE

    • library WORK, STD;

    • use STD.STANDARD.ALL;

  • Copyright 2006 - Joanne DeGroat, ECE, OSU


    A final note l.jpg
    A final note

    • If you write a package and analyze it into library WORK, to use the declarations there you need to have a use clause.

      • use WORK.TriState.TRI,WORK.TriState.BitVal;

      • Or could have use.WORK.TriState.ALL;

      • This makes the type TRI and the function BitVal visible to the current design unit in addition to STD.STANDARD.ALL

      • EXAMPLE SLIDE for type compatability

    Copyright 2006 - Joanne DeGroat, ECE, OSU


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