1 / 5

CASE STUDY OF A MULTYCYCLE DATAPATH

CASE STUDY OF A MULTYCYCLE DATAPATH. 32. 0. Mux. 0. Mux. 1. Instruction Reg. ALU Out. 32. 0. 1. Mux. 32. 32. 1. ALU Control. Mux. 1. 0. Extend. 16. 4. << 2. Alternative Multiple Cycle Datapath (In Textbook). Minimizes Hardware: 1 memory, 1 ALU. PCWr. PCWrCond. PCSrc.

hop
Download Presentation

CASE STUDY OF A MULTYCYCLE DATAPATH

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. CASE STUDY OF A MULTYCYCLE DATAPATH

  2. 32 0 Mux 0 Mux 1 Instruction Reg ALU Out 32 0 1 Mux 32 32 1 ALU Control Mux 1 0 Extend 16 4 << 2 Alternative Multiple Cycle Datapath (In Textbook) • Minimizes Hardware: 1 memory, 1 ALU PCWr PCWrCond PCSrc Zero ALUSrcA IorD MemWr IRWr RegDst RegWr 1 Mux 32 PC 0 PC Zero 32 Rs Ra 32 Address 5 32 Rt 32 Rb busA A ALU Ideal Memory 32 Reg File 5 Rt 0 Rw 32 32 B 32 Rd 1 Mem Data Reg Din Dout busW busB 2 32 3 MemRd Imm 32 ALUOp MemtoReg ALUSrcB

  3. State Diagram: operations for Each Cycle Logic Immediate IR ¬ Mem[PC] State= 00000 A ¬ R[rs] B ¬ R[rt] PC ¬ PC + 4 State= 00010 ALUout ¬ A Op ZeroExt[imm16] State= 01010 R[rt] ¬ ALUout State= 01011 Go Next state= 00000 R-Type IR ¬ Mem[PC] State= 00000 A ¬ R[rs] B ¬ R[rt] PC ¬ PC + 4 State= 00001 ALUout ¬ A Op B State= 01000 R[rd] ¬ ALUout State= 01001 Go Next state= 00000 Store IR ¬ Mem[PC] State= 00000 A ¬ R[rs] B ¬ R[rt] PC ¬ PC + 4 State= 00100 ALUout ¬ A Op SignExt[imm16] State= 01111 Mem[R]¬ALUout State= 010000 Go Next state= 00000 Cond-Branch IR ¬ Mem[PC] State= 00000 A ¬ R[rs], B ¬ R[rt], Z[R[rs]-R[rt]] PC ¬ PC + 4 State= 00101 PC ¬ (PC + 4) + (Z=1) (SignExt(imm16) x4) State= 010001 Go Next state= 00000 Branch IR ¬ Mem[PC] State=00000 PC ¬ [PC + 4]28-31, (IMM-26)26] State= 00110 Go Next State 00000 Load IR ¬ Mem[PC] State= 00000 A ¬ R[rs] B ¬ R[rt] PC ¬ PC + 4 State= 00011 ALUout ¬ A Op SignExt[imm16] State= 01100 MDR ¬ ALUout State= 01101 R[rt] ¬ MDR State= 01110 Go Next state= 00000 IF ID EX/M WB

  4. IF Current Op field Z Next IR PC Ops Exec Mem Write-Back State A B Ex Sr ALU S R W M M-R Wr Dst ID BEQ R I LW SW

  5. IF Current Op field Z Next IR PC Ops Exec Mem Write-Back State A B Ex Sr ALU S R W M M-R WrDst 00000 XXXX ? 00001 1 00001 R-type x 01000 1 1 00010 I-type x 01010 1 1 00011 LW x 01100 1 1 00100 SW x 01111 1 1 00101 BEQ x 00111 1 1 00110 Jump x 00000 1 1 00111 xxxxxx x 00000 1 1 01000 xxxxxx x 01001 0 1 fun 1 01001 xxxxxx x 00000 1 0 0 1 1 01010 xxxxxx x 01011 0 0 or 1 01011 xxxxxx x 00000 1 0 0 1 0 01100 xxxxxx x 01101 1 0 add 1 01101 xxxxxx x 01110 1 0 1 01110 xxxxxx x 00000 1 0 1 1 0 01111 xxxxxx x 10000 1 0 add 1 10000 xxxxxx x 00000 1 0 0 1 ID BEQ R I LW SW

More Related