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iBob Tutorial. Dejan Markovic, Zhengya Zhang {dejan, zhengya}@eecs.berkeley.edu. The iBob. Xilinx (Virtex2p) emulation board. IO. 5V DC. XSG Output: *.prj. Step 1: SysGen. Setup Part as specified in the screen shot Synthesis tool FPGA clock (up to 200MHz). Synplify Output: *.edf.

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Ibob tutorial

iBob Tutorial

Dejan Markovic, Zhengya Zhang

{dejan, zhengya}@eecs.berkeley.edu


The ibob
The iBob

  • Xilinx (Virtex2p) emulation board

IO

5V DC


Step 1 sysgen

XSG Output:

*.prj

Step 1: SysGen

  • Setup

    • Part as specified in the screen shot

    • Synthesis tool

    • FPGA clock (up to 200MHz)


Step 2 synplify pro

Synplify Output:

*.edf

Step 2: Synplify Pro

  • Create shortcut on your local machine

    • Open existing project: SYSGEN/*.prj

    • Run


Step 3 project navigator
Step 3: Project Navigator

  • Programs / XilinxISE / Project Navigator

    • Open the *.npl file from <design>/SYSGEN


Step 4 pin assignment
Step 4: Pin Assignment

  • Uncheck “read-only” on the *.npl file

  • User constraints / Create Timing Constraints

  • User constraints / assign package pins

    • a) Edit user constraint (use package I/O look-up table)

      (note: use “gpio” pins information )

    • b) it is easier to edit this file in Wordpad and using pinout table from the next slide)

\\hitz\designs\BEE\tutorials\*.xls (pin assignment)


Ibob pinout map
iBob Pinout Map

gpio2

gpio3

gpio1

gpio0

(top)

(top)

(top)

(top)

gnd

F14 (19)

gnd

K12 (19)

gnd

F18(19)

gnd

J20 (19)

gnd

E14

gnd

J12

gnd

G18

gnd

K20

gnd

C14

gnd

H13

gnd

K18

gnd

C24

gnd

C13

gnd

G13

gnd

L18

gnd

D24

gnd

L16

gnd

D9

gnd

D19

gnd

D23

gnd

K16 (14)

gnd

C9 (14)

gnd

E19 (14)

gnd

D22 (14)

gnd

G15

gnd

K14

gnd

F19

gnd

G21

gnd

F15

gnd

J14

gnd

G19

gnd

H21

gnd

D14

gnd

F13

gnd

H19

gnd

D25

gnd

D15

gnd

E13

gnd

J19

gnd

E25

gnd

J16 (9)

gnd

E10 (9)

gnd

D20 (9)

gnd

E22 (9)

gnd

H16

gnd

D10

gnd

D21

gnd

F22

gnd

G16

gnd

H14

gnd

F20

gnd

J21

gnd

F16

gnd

G14

gnd

G20

gnd

K21

gnd

E16

gnd

D13

gnd

K19

gnd

C26

gnd

D16 (4)

gnd

D12 (4)

gnd

L19 (4)

gnd

D26 (4)

L17

gnd

C22

gnd

D11

gnd

G22

gnd

gnd

K17

gnd

C11

gnd

C21

gnd

H22

gnd

G17

gnd

K15

gnd

E21

gnd

J23

gnd

F17 (0)

gnd

J15 (0)

gnd

F21 (0)

gnd

K23 (0)

J8

J9

J7

J6


Pin assignment
Pin Assignment

  • *.ucf file

defined in *.ncf

file which should

be empty after you

copy it here

iBob has diff Clk,

and this needs to

be defined before

clk_out pin


Edit des clk wrapper vhd
Edit <des>_clk_wrapper.vhd

  • Specify Clk (diff -> single ended)

entity sq_clk_wrapper is port (

ce: in std_logic := '1';

clk_n: in std_logic;

clk_p: in std_logic;

clk_out: out std_logic;

as: out std_logic_vector(13 downto 0);

zs: out std_logic_vector(15 downto 0) );

end sq_clk_wrapper;

diff  single ended Clk,

architecture structural of sq_clk_wrapper is

component IBUFGDS

port (O : out STD_ULOGIC;

I : in STD_ULOGIC;

IB : in STD_ULOGIC);

end component;

component sq

<next page>


Edit des clk wrapper vhd cont
Edit <des>_clk_wrapper.vhd (Cont.)

  • Assign port map

signal clk: std_logic;

begin

CLOCK_BUFFER : IBUFGDS

port map (O => clk,

I => clk_p,

IB => clk_n);

clk_out <= clk;

clk_sysgen <= clk;

as <= as_x_0;

zs <= zs_x_0;

port map


Step 5 implement design
Step 5: Implement Design

  • Right click on “Implement Design” / Run


Step 6 generate bit file

Output:

*.bit

Step 6: Generate *.bit File

  • Copy bit file to a local machine


Step 7 program fpga
Step 7: Program FPGA

  • Go to the lab and program *.bit file into an FPGA

    • Run Xilinx ISE / IMPACT from local machine


Ibob pinout table

iBob pinout table

- Tutorial -


Ibob pinout map1
iBob Pinout Map

gpio2

gpio3

gpio1

gpio0

(top)

(top)

(top)

(top)

gnd

F14 (19)

gnd

K12 (19)

gnd

F18(19)

gnd

J20 (19)

gnd

E14

gnd

J12

gnd

G18

gnd

K20

gnd

C14

gnd

H13

gnd

K18

gnd

C24

gnd

C13

gnd

G13

gnd

L18

gnd

D24

gnd

L16

gnd

D9

gnd

D19

gnd

D23

gnd

K16 (14)

gnd

C9 (14)

gnd

E19 (14)

gnd

D22 (14)

gnd

G15

gnd

K14

gnd

F19

gnd

G21

gnd

F15

gnd

J14

gnd

G19

gnd

H21

gnd

D14

gnd

F13

gnd

H19

gnd

D25

gnd

D15

gnd

E13

gnd

J19

gnd

E25

gnd

J16 (9)

gnd

E10 (9)

gnd

D20 (9)

gnd

E22 (9)

gnd

H16

gnd

D10

gnd

D21

gnd

F22

gnd

G16

gnd

H14

gnd

F20

gnd

J21

gnd

F16

gnd

G14

gnd

G20

gnd

K21

gnd

E16

gnd

D13

gnd

K19

gnd

C26

gnd

D16 (4)

gnd

D12 (4)

gnd

L19 (4)

gnd

D26 (4)

L17

gnd

C22

gnd

D11

gnd

G22

gnd

gnd

K17

gnd

C11

gnd

C21

gnd

H22

gnd

G17

gnd

K15

gnd

E21

gnd

J23

gnd

F17 (0)

gnd

J15 (0)

gnd

F21 (0)

gnd

K23 (0)

J8

J9

J7

J6


Sq experiment
SQ Experiment

NET clk_out LOC = K12;

NET "zs(15)" LOC="K23";

NET "zs(14)" LOC="J23";

NET "zs(13)" LOC="H22";

NET "zs(12)" LOC="G22";

NET "zs(11)" LOC="D26";

NET "zs(10)" LOC="C26";

NET "zs(9)" LOC="K21";

NET "zs(8)" LOC="J21";

NET "zs(7)" LOC="E22";

NET "zs(6)" LOC="E25";

NET "zs(5)" LOC="D25";

NET "zs(4)" LOC="H21";

NET "zs(3)" LOC="G21";

NET "zs(2)" LOC="D22";

NET "zs(1)" LOC="D23";

NET "zs(0)" LOC="D24";

NET "as(13)" LOC="C24";

NET "as(12)" LOC="K20";

NET "as(11)" LOC="J20";

NET "as(10)" LOC="F21";

NET "as(9)" LOC="E21";

NET "as(8)" LOC="C21";

NET "as(7)" LOC="C22";

NET "as(6)" LOC="L19";

NET "as(5)" LOC="K19";

NET "as(4)" LOC="G20";

NET "as(3)" LOC="F20";

NET "as(2)" LOC="D21";

NET "as(1)" LOC="D20";

NET "as(0)" LOC="J19";

gpio0

gnd

J20 (19)

gnd

K20

gnd

C24

gnd

D24

gnd

D23

gnd

D22

gnd

G21

gnd

H21

Z<15:0>

gnd

D25

gnd

E25

gnd

E22

exclude

gnd

F22

gnd

J21

gnd

K21

gnd

C26

gnd

D26

gnd

G22

gnd

H22

gnd

J23

gnd

K23 (0)

J6


Logic analyzer

Logic Analyzer

- Tutorial -


Main window select setup trig
Main Window  Select / Setup & Trig



Setup and trigger window trigger
Setup and Trigger Window / Trigger

  • Edit switching threshold


Select listing
Select  Listing

  • File/Print to file/ ftp to local disk


Sampling problem eye finder
Sampling Problem: Eye Finder

  • Eye opening scattered around Clk edge


Results
Results

  • Sampling inconsistency


Results1
Results

  • Look Familiar?




Well known result
Well Known Result

  • Experimentally justified logo…

1/

Q

R

T

S

today


Results4
Results

  • “The CITY” logo


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