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Toward a general purpose computer

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Toward a general purpose computer

Example: Game of Life

Solve Cell

For Each Cell

For Each Line

Matrix

Generation

Line

Cell

Solve Cell

For Each Cell

For Each Line

- Generation Module
- Matrix Module
- Line Module
- Cell Module

- CurrentGen = 0
- Solve for current Matrix
- CurrentGen++
- If CurrentGen < MAX_GEN
goto 2

0. j = 1

1. Calculate line (j)

2. If j < MAX_LINE

2.1 j++

2.2 goto 1.

3. STOP

0. i = 0, tmp = 0

1. Calculate Cell i.

2. If alive, set location i in tmp to alive

3. If i < MAX_CELL

3.1 i++

3.2 goto 1.

4. Store tmp in :

even generation: i+16odd generation : i-16

0. N = Count_Neighbors(i,j-1,false)

1. N = N+Count_Neighbors(i,j,true)

2. N = N+Count_Neighbors(i,j+1,false)

3. If N > MIN && N < MAX

3.1 Return alive

4. Return dead

0. N = 0

1. If alive in location [i-1,j]: N=N+1

2. If not center:

2.1 If alive in location [i,j]: N=N+1

3. If alive in location [i+1,j]: N=N+1

4. Return N

Algorithm

How to do?

What to do?

The operation itself

control

Operations:

- Add
- Subtract

The Operation itself

(i-1) location

Return Number of Neighbor: N

CountNeighbors

Alive: 0..010..0

CellAlive

Return

Dead: 0000000

Calculate Line

Return the line

Solve Matrix

The matrix

Generation

The Operation itself

If alive in location [i-1,j]

decode(i-1) = 0001000

AND

Line (j) = 00010100

decode(i-1) = 0001000

AND

Line (j) = 00000100

Result = 00000000

Result = 00010000

Non Zero – cell in

location i is alive

Zero – cell in

location i is dead

The Operation itself

If alive in location [i-1,j]

Alive if AND(line,decode(i-1))

is not zero

The Operation itself

Operations:

- Add
- Subtract
- The logic AND + Check if zero

The Operation itself

The Operation itself

StatusBit

The Operation itself

InputB

InputA

ALU

Op

StatusBit

isZero

Reg1

Reg2

Reg3

Regn

Reg1

1

ReadA

ReadB

Reg2

2

Reg3

Connected like MUX 1

Regn

Reg1

1

ReadA

ReadB

Reg2

2

Write Address

Reg3

Write Data

Regn

Decoder

Write

Enable

Registers

Data 1 Address

Data 1

Data 2 Address

Data 2

WriteAddress

Write Data

Write

Registers

Data 1 Address

Op

Data 2 Address

WriteAddress

ALU

Extend 1to 16

MUX

R0R1

Write

2

0

ExternalInput

1

The Operation itself

If alive in location [i+1,j]: N=N+1

Algorithm instruction

Instruction

- Tmp = is zero[AND(Currentline,
- decode(i+1))]

The Operation itself

Tmp = is zero[AND(line,decode(i-1))]

Instruction

t0. Tmp = i-1

t1. Tmp = decode(Tmp)

t2. controlVariable = is zero[AND(CurrentLine, Tmp)]

Micro-Instruction

The Operation itself

- Tmp = i+1
- Tmp = decode(Tmp)
- controlVariable = is zero[AND(CurrentLine, Tmp)]

Micro-Instruction

i

t0. Data 1 Address = 1Data 2 Address = 5

WriteAddress = 3

Write = 1

Op = 01R0R1 = 01

1

tmp

Subtract

The result of the ALU

The Operation itself

- Tmp = i+1
- Tmp = decode(Tmp)
- controlVariable = is zero[AND(CurrentLine, Tmp)]

Micro-Instruction

tmp

t1. Data 1 Address = 3Data 2 Address = 0

WriteAddress = 4

Write = 1

Op = 11R0R1 = 01

Irrelevant

tmp

Decode

The result of the ALU

The Operation itself

- Tmp = i+1
- Tmp = decode(Tmp)
- controlVariable = is zero[AND(CurrentLine, Tmp)]

Micro-Instruction

Line in register i

t2. Data 1 Address = 0Data 2 Address = 3

WriteAddress = 6

Write = 1

Op = 10R0R1 = 00

tmp

controlVariable

And

The zero status bit

The Operation itself

Algorithmic Instruction

Instruction

Micro-Instruction

Micro-Instruction

Instruction

Micro-Instruction

Micro-Instruction

Timing Variables

Instruction

t0: Micro-Instruction

tn: Micro-Instruction

Each micro

instruction = 1 cycle

Instruction

t0:Micro-Instruction

tn: Micro-Instruction

CP

t0

t1

t2

t3

One instruction

Register 4bits

CP

t0

t15

1

Decoder

Adder

0000

0001

0010

0011

0100

0101

0110

0111

1000

0000

0001

0010

0011

0100

0101

0110

0111

1000

ROM Output

ROM Input

Center

Register 7 (16bits)

Control variable (16bits)

The current state

(4 bits)

The current timing variable(1 bits)

ROM Output

ROM Input

Data 1 Address

Data 2 Address

Write-Data MUX control

WriteAddress

Write

ALU Operation

ROM Output

ROM Input

t0. Tmp = i+1

t1. Tmp = decode(Tmp)

t2. controlVariable = is zero[AND(CurrentLine, Tmp)]

t3. do nothing

ROM Output

ROM Input

t0. Tmp = i+1

t1. Tmp = decode(Tmp)

t2. controlVariable = is zero[AND(CurrentLine, Tmp)]

t3. do nothing

ROM Output

ROM Input

t0. Tmp = i+1

t1. Tmp = decode(Tmp)

t2. controlVariable = is zero[AND(CurrentLine, Tmp)]

t3. do nothing

ROM Output

ROM Input

t0. Tmp = i+1

t1. Tmp = decode(Tmp)

t2. controlVariable = is zero[AND(CurrentLine, Tmp)]

t3. do nothing

0000

0001

0010

Current State = 0001

t0. Set Current State 0001

t1. Set Current State 0001

t2. Set Current State 0001

t3. If ControlVariable=1

Set Current State 0010

t3. If ControlVariable=0

Set Current State 0011

0011

0100

0101

0110

0111

1000

ROM Input

ROM Output

Here is the branch.

Timing Variable

CurrentState

Current State

Next State

ROM

Op

Write

Registers

D1

D2

WA

WriteData

ALU

MUX

R0R1

Extend 1to 16

Result

zerobit

1