MODULE II. MICROCONTROLLERS & EMBEDDED SYSTEMS. STACK IN8051. Section of RAM Store information temporarily Data or address Needs stack due to limited number of registers Register inside CPU to point to the stack SP – stack pointer to access the stack SP is 8- bits wide.
8051 is powered up , SP register contains values 07.
RAM locations 08 is the first location used for the stack.
Storing of CPU register to stack – PUSH
Pulling the contents from stack to CPU register – POP
SP is very critical when push and pop actions are performed
Used to select bank registers
PSW5 and PSW1 bits are general purpose status flag bits
Can be used by the programmer for any purpose
Ie. User definable
Dual role of port2
Some timers do this by software and hardware
8051 timers have both controls
When GATE= O, S/W start and stop are controlled by TR bits of TCON register
This is achieved by the instructions SETB TR1 and CLRB TR1 for timer 1.
These instruction s start and stop the timers as long as GATE = O.
When GATE = 1 the starting and stoping of Timers are done by means of external H/W.
When a byte is written into SBUF, it is framed with the start and stop bits and sends serially via the TxD pin
SCON (serial port control) reg