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VEPIX53: further developments. Sara Marconi , Elia Conti. From Elia’s presentation: RD53 2nd WG3 Meeting – 15/01/2014. What’s next? Implement two different architectures in VEPIX53 DUT : Zero-suppressed shared FIFO (minor modifications from current version)

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Vepix53 further developments

VEPIX53:

further developments

Sara Marconi , Elia Conti


Vepix53 further developments

From Elia’s presentation: RD53 2nd WG3 Meeting – 15/01/2014

  • What’s next?

    • Implement two different architectures in VEPIX53 DUT:

    • Zero-suppressed shared FIFO (minor modifications from current version)

    • Local buffers with latency counters (FE-I4 for reference)

    • At which description level? (behavioral/TLM)

    • Add further features in verification components for retrieving buffering performance indicators

    • Perform simulation with both randomized and MC data inputs


Vepix53 further developments

VEPIX53: first analysis with profiler (I)

  • Increasing array dimension (20x20) – with still 1 PR:

    Memory Usage - 24.6M program + 227.9M data + 3.0M profile = 255.4M total

    CPU Usage - 0.4s system + 1.9s user = 2.3s total (41.3% cpu)

    ------------------------------------------------------------

    Stream Counts (897 hits total)

    ------------------------------------------------------------

    %hits #hits #inst name

    35.7 320 [ 1] Scope unmblk1 (file: ../source/VerificationEnvironment/analysis/sv/analysis_ref_model.sv, line: 96 in worklib.analysis_pkg [package])

    13.9 125 [ 1] Non-blocking Assignment (file: ../source/PixelChipHarness/dut/PixelRegion.sv, line: 66 in plib.PixelRegion [module])

    5.6 50 [ 1] Function convert2string (file: ../source/VerificationEnvironment/readout/sv/readout_transfer.sv, line: 28 in worklib.readout_pkg [package])

    ------------------------------------------------------------

    Assertion Summary Counts (297 hits, 33.1% of total)

    ------------------------------------------------------------

    %hits #hits #inst name

    20.0 179 [ 0] __assert_11 (immediate assert stmt, file: ../source/VerificationEnvironment/analysis/sv/analysis_ref_model.sv, line: 101)

    13.2 118 [ 0] __assert_12 (immediate assert stmt, file: ../source/VerificationEnvironment/analysis/sv/analysis_ref_model.sv, line: 102)

    ------------------------------------------------------------

    Time in Randomize Calls (32 hits, 3.6% of total)

    ------------------------------------------------------------

    rnc(msec) svrnc(msec) #calls name

    1.5 40.8 100 ../source/VerificationEnvironment/hit/sv/hit_master_seq_lib.sv, line: 129

    5.9 12.1 100 ../source/VerificationEnvironment/trigger/sv/trigger_master_seq_lib.sv, line: 80

    7.7 0.5 1 /vlsicad/soft2013lnx/INCISIV_12.10HF005/tools/uvm-1.1/uvm_lib/uvm_sv/sv/seq/uvm_sequencer_base.svh, line: 1377

    0.4 0.2 1 ../source/VerificationEnvironment/top/sv/top_virtual_seq_lib.sv, line: 86

    0.2 0.2 1 ../source/VerificationEnvironment/top/sv/top_virtual_seq_lib.sv, line: 87

    Is it reasonable to check per each BX cycle if analog/digital parts of the pixel are busy? (still timed model)


Vepix53 further developments

VEPIX53: first analysis with profiler (II)

  • Eliminating checkings in reference model (PR 20x20):

    MemoryUsage - 24.6M program + 227.9M data + 3.0M profile = 255.5M total

    CPU Usage - 0.2s system + 1.3s user = 1.5s total (73.6% cpu)

    ------------------------------------------------------------

    Stream Counts (552 hits total)

    ------------------------------------------------------------

    %hits #hits #inst name

    21.9 121 [ 1] Non-blocking Assignment (file: ../source/PixelChipHarness/dut/PixelRegion.sv, line: 66 in plib.PixelRegion [module])

    9.6 53 [ 1] Function convert2string (file: ../source/VerificationEnvironment/readout/sv/readout_transfer.sv, line: 28 in worklib.readout_pkg [package])

    8.3 46 [ 1] Function match_scope (file: /vlsicad/soft2013lnx/INCISIV_12.10HF005/tools/uvm-1.1/uvm_lib/uvm_sv/sv/base/uvm_resource.svh, line: 408 in worklib.uvm_pkg [package])

    8.0 44 [ ] Method SSS_MT_SVHASSIGN (method)

    6.2 34 [ 1] Anonymous continuous assignment (file: ../source/PixelChipHarness/dut/PixelChip.sv, line/pos: 56/23 in plib.PixelChip [module])

    ------------------------------------------------------------

    Assertion Summary Counts (1 hits, 0.2% of total)

    ------------------------------------------------------------

    %hits #hits #inst name

    0.2 1 [ 0] __assert_10 (immediate assert stmt, file: ../source/VerificationEnvironment/analysis/sv/analysis_ref_model.sv, line: 94)

    ------------------------------------------------------------

    Time in Randomize Calls (37 hits, 6.7% of total)

    ------------------------------------------------------------

    rnc(msec) svrnc(msec) #calls name

    2.9 44.7 100 ../source/VerificationEnvironment/hit/sv/hit_master_seq_lib.sv, line: 129

    5.8 11.9 100 ../source/VerificationEnvironment/trigger/sv/trigger_master_seq_lib.sv, line: 80

    8.7 0.5 1 /vlsicad/soft2013lnx/INCISIV_12.10HF005/tools/uvm-1.1/uvm_lib/uvm_sv/sv/seq/uvm_sequencer_base.svh, line: 1377

  • Improvement

  • but going to 40x40 – not clear error:

    csi-ncsim - CSI: *F,INTERR: INTERNAL EXCEPTION

    Observed simulation time : 0 FS + 0

    -----------------------------------------------------------------

    The tool has encountered an unexpected condition and must exit.

    Contact Cadence Design Systems customer support about this

    problem and provide enough information to help us reproduce it,

    including the logfile that contains this error message.

    TOOL:ncsim(64)12.10-s005

    HOSTNAME: lnxmic13

    OPERATING SYSTEM: Linux 2.6.18-371.3.1.el5 #1 SMP Fri Dec 6 08:34:45 CET 2013 x86_64

    MESSAGE: Unexpected signal #11, program terminated (null)

    ----------------------------------------------------------------


Vepix53 further developments

VEPIX53: Main questions

  • DUT model for architectural studies:

    • TLM or behavioral ?

    • Timed or untimed ?

    • performance indicators ?

  • On the VE side:

    • keep TOT-DUT busy at reference model level?

    • use the TLM to RTL conversion ?

    • move synchronization at the sequence level (not in driver)?

    • making it capable of verifying existing pixel chips is a priority (i.e. FEI4)? (or keep it simple and focus on architectural studies/TLM/clustering/...)

      • slow control interface missing (UVM registers eventually to be used)

      • command interface missing (e.g. trigger protocol specific)

      • protocol specific readout

      • etc…


Backup slides

BACKUP SLIDES


Tlm verification environment ve

TLM Verification Environment (VE)

Configuration

object

TLMTest

Top-level virtual sequence

Configuration

object

Configuration

object

Sequence

library

Pixel ASIC

TLM DUT

Input

agent

Output agent

Output data

interface

Discriminator

interface

Configuration

object

TFC

Agent

Slow

Control

Agent

TFC

interface

Slow control

interface

Sequence

library

Sequence

library

Analysis

Components

Configuration

object

RD53 - WG3 - T. Poikela


Connecting tlm to rtl

Connecting TLM to RTL

Verification component

TLM2RTL -adaptor

Sequencer

TLMDriver

RTL

Driver

Sequence

library

Configuration

object

TLM

Monitor

RTL

Monitor

Configuration

object

Coverage

Collector

Coverage

Collector

TLM Agent

RTL Agent

Everything works at transaction level.

Only this part is pin-level specific.

RD53 - WG3 - T. Poikela


Reusing tlm ve at rtl

Reusing TLM VE at RTL

RTLTest extends TLMTest

Top-level virtual sequence

Configuration

object

Configuration

object

Sequence

library

Pixel

ASIC

RTL

DUT

Input

agent

Output agent

TL2

RTL

TL2

RTL

Configuration

object

TFC

agent

TL2

RTL

Slow

Control

agent

TL2

RTL

Sequence

library

Sequence

library

Analysis Components

Configuration

object

TL2RTL components are chip/protocol specific

interface -construct

RD53 - WG3 - T. Poikela


How does this fit into rd53 wg3

How does this fit into RD53 WG3?

  • TLM-based VE quite generic, everything at transaction level => starting platform for more general simulations

  • Designers of particular chips can build their bit-level interfaces on top of TLM

  • Models above RTL abstraction faster and easier to develop (and modify)

  • Several users => Well-defined interfaces (like TLM) make model integration easier

  • Probably the biggest challenge: Make something useful that is fast to learn (documentation + examples!)

RD53 - WG3 - T. Poikela


Vepix53 further developments

VEPIX53:

A Verification Environment for the RD53 pixel chip

Elia Conti, Sara Marconi


Vepix53 further developments

OUTLINE

  • Block diagram of the verification environment

  • Project organization

  • DUT

  • Interfaces

  • Verification components

    • Hit

    • Trigger

    • Readout

    • Flag

    • Top

  • Command line scripts


Vepix53 further developments

Block diagram of the verification environment

  • top test lib

  • top base test

  • top test1,2…

top env

analysisenv

hit env

readoutenv

trigger env

top virtualsequencer

PixelChipHarness

Clock and resetgenerator

PixelChip

DUT

hit_if

analysis_if

trig_if

readout_if

PixelChipInterfaces


Vepix53 further developments

Project organization

  • VEPIX53 v1.0

    • source (source files)

    • PixelChipHarness

    • VerificationEnvironment

    • work

    • command line scripts

    • simulation library


Vepix53 further developments

DUT

Pixel Chip

PixelChipHarness

Pixel Region (PR)

PR buffer

Pixel matrix

ToA

HITS

HIT

PACKETS

ToT

ToT

conv.

Digital

PUC

TRIGGERLOGIC

.....

.....

.....

TRIGGER

TIME TAG

END OF COLUMN

(externalToAcounter)

PIXEL BUSY FLAGS

PR BUFFER FULL FLAG

PixelChipHarness.sv

PixelChip.sv

PixelRegion.sv

EOC.sv

PixelUnitCell.sv

ToT_Converter.sv

Digital_PixelUnitCell.sv

BufferTriggerLogic.sv

PixelConfigReg.sv

PixelSyncLogic.sv

PixelCore.sv

PixelFSM.sv

PixelCounters.sv


Vepix53 further developments

Interfaces

Pixel Chip

Pixel Region (PR)

PR buffer

Pixel matrix

ToA

HITS

HIT

PACKETS

ToT

ToT

conv.

Digital

PUC

TRIGGERLOGIC

.....

.....

.....

TRIGGER

TIME TAG

END OF COLUMN

(externalToAcounter)

PIXEL BUSY FLAGS

PR BUFFER FULL FLAG

  • Hit interface

  • analog_hit

  • Trigger interface

  • trigger

  • Readout interface

  • buffer_out

  • eoc_ext_count

  • Analysis interface

  • ToT_conv_busy

  • DUT_busy

  • buffer_full


Vepix53 further developments

Verification components

  • VerificationEnvironment

    • top

    • hit

    • trigger

    • readout

    • analysis


Vepix53 further developments

Hit verification component (I)

  • hit_if.sv

  • physical hit interface

  • hit_config.sv

  • multiple configuration classes for the hit verification component

  • hit_pkg.sv

  • package for the hit verification component (collects includes)

  • hit_env.sv

  • wraps hit master agent

  • hit_master_agent.sv – contains

  • configuration object

  • sequencer

  • driver

  • monitor

hit env

hit master agent

hit master

sequencer

hit master driver

Analoghits

hit master seq lib

hit _config

hit monitor

hit _master_config


Vepix53 further developments

Hit verification component (II)

  • hit_master_sequencer.sv

  • hit_master_seq_lib.sv

  • library of sequences that can be run on the hit master sequencer

  • hit_transfer.sv

  • transaction classes used in the hit verification component:

    • hit_trans (generation side)

    • Hit_Time_Trans (monitoring side)

  • hit_master_driver.sv

  • translates hit_trans transactions into physical signals that are injected in the DUT

  • hit_monitor.sv

  • senses physical signal on hit_if interface and builds Hit_Time_Trans transactions

hit env

hit master agent

hit master

sequencer

hit master driver

Analoghits

hit master seq lib

hit _config

hit monitor

hit _master_config


Vepix53 further developments

Trigger verification component (I)

  • trigger_if.sv

  • physical trigger interface

  • trigger_config.sv

  • multiple configuration classes for the trigger verification component

  • trigger_pkg.sv

  • package for the trigger verification component (collects includes)

  • trigger_env.sv

  • wraps trigger master agent

  • trigger_master_agent.sv – contains

  • configuration object

  • sequencer

  • driver

  • monitor

trigger env

trigger master seq lib

trigger_config

trigger master agent

trigger _master_config

trigger master

sequencer

trigger master driver

trigger monitor


Vepix53 further developments

Trigger verification component (II)

  • trigger_master_sequencer.sv

  • trigger_master_seq_lib.sv

  • library of sequences that can be run on the trigger master sequencer

  • trigger_transfer.sv

  • transaction classes used in the trigger verification component:

    • trigger_trans (generation side)

    • Trigger_Time_Trans (monitoring side)

  • trigger_master_driver.sv

  • translates trigger_trans transactions into physical signals that are injected in the DUT

  • trigger_monitor.sv

  • senses physical signal on trigger_if interface and builds Trigger_Time_Trans transactions

trigger env

trigger master seq lib

trigger_config

trigger master agent

trigger _master_config

trigger master

sequencer

trigger master driver

trigger monitor


Vepix53 further developments

Readout verification component

  • readout_if.sv

  • physical readout interface

  • readout_pkg.sv

  • package for the readout verification component (collects includes)

  • readout_env.sv

  • wraps readout master agent

  • readout_master_agent.sv

  • contains readout monitor

  • readout_transfer.sv

  • contains readout_trans transaction class used in readout verification component

  • readout_monitor.sv

  • senses physical signal on readout_ifinterface and builds readout_transtransactions

readoutenv

readout master agent

readout monitor


Vepix53 further developments

Analysis verification component (I)

  • analysis_if.sv

  • analysis interface containing virtualized flag signals

  • analysis_pkg.sv

  • package for the analysis verification component (collects includes)

  • analysis_env.sv

  • wraps analysis master agent

  • analysis_master_agent.sv

  • contains analysis monitor

  • analysis_transfer.sv

  • contains analysis_trans transaction class used in analysis verification component

  • analysis_monitor.sv

  • senses flag signals on analysis_ifinterface and builds analysis_transtransactions

analysisenv

analysisref. model

analysisscoreboard

hit

analysis monitor

readout

trigger

analysis master agent


Vepix53 further developments

Analysis verification component (II)

  • analysis_ref_model.sv

  • reference model of the pixel chip DUT

analysisreference model

actual

reference model

lost hit

selection

predicted

DUT output

uvm_tlm_analysis_fifo

uvm_tlm_fifo

hit

uvm_tlm_analysis_fifo

flags

uvm_tlm_analysis_fifo

trigger


Vepix53 further developments

Analysis verification component (III)

  • analysis_scoreboard.sv

  • scoreboard of the verification environment

analysisscoreboard

uvm_in_order_class_comparator

predicted

DUT output

actual

DUT output


Vepix53 further developments

Top level components

  • top_pkg.sv

  • includes class defines

  • imports packages of all verification components used in the environment

  • includes all top level classes

  • top_env.sv – builds and connects

  • hit verification component

  • trigger verification component

  • top virtual sequencer

  • readout verification component

  • flag verification component

  • top_virtual_sequencer.sv

  • contains flag monitor

  • top_virtual_seq_lib.sv

  • sequences to be run in the top virtual sequencer

top env

top virtual seq lib

top virtualsequencer


Vepix53 further developments

Top level tests

top env

  • top_test_pkg.sv

  • wraps all low level and top level packages

  • also includes top level test library

  • top_test_lib.sv

  • top_base_test.sv

  • top_test1.sv

  • top_test2.sv

  • PixelChip_tb.sv

  • top level module

  • instantiates the harness (containing the DUT)

  • registers virtual interfaces

  • top test lib

  • top base test

  • top test1,2…

top virtual seq lib

top virtualsequencer


Vepix53 further developments

Command line scripts

  • Implemented functionality for Multi-Snapshot Incremental Elaboration (MSIE) (useful to avoid re-elaboration each time testbenchis modified)

  • make plib

  • compile DUT library plib

  • make run1

  • compilation and elaboration of primary snapshot (DUT)

  • make run2

  • compilation and elaboration of the secondary snapshot (TESTBENCH)


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