Effects of on chip inductance on power distribution grid
This presentation is the property of its rightful owner.
Sponsored Links
1 / 17

Effects of On-chip Inductance on Power Distribution Grid PowerPoint PPT Presentation


  • 91 Views
  • Uploaded on
  • Presentation posted in: General

Effects of On-chip Inductance on Power Distribution Grid. Atsushi MuramatsuKyoto Univ. Masanori HashimotoOsaka Univ. Hidetoshi OnoderaKyoto Univ. [email protected] chip. bonding wire. bump ball. chip. Inductance in power grid analysis. Advance in packages. Conventionally

Download Presentation

Effects of On-chip Inductance on Power Distribution Grid

An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -

Presentation Transcript


Effects of on chip inductance on power distribution grid

Effects of On-chip Inductance on Power Distribution Grid

Atsushi MuramatsuKyoto Univ.

Masanori HashimotoOsaka Univ.

Hidetoshi OnoderaKyoto Univ.

[email protected]


Inductance in power grid analysis

chip

bonding wire

bump ball

chip

Inductance in power grid analysis

Advance in packages

  • Conventionally

    • Inductance of package and bonding

      • dominant

      • considered

    • Inductance of on-chip wire

      • many elements yet small

      • not considered

  • Recently

    • Increase in clock freq.

      • higher freq. component of noise

      • wL increases as freq. increases

    • Reduction in L of package and bonding

      • Relatively on-chip L increases

QFP

FCBGA

(Bump Array)

Q: on-chip inductance important?


Previous works

Previous works

  • [Mezhiba, Kluwer 2004]

    • Outline of on-chip inductance aware analysis

    • Noise propagates as a wave

  • [Y.-M. Lee, TCAD02]

    • Fast simulation based on transmission line theory

  • [W.H. Lee, ISQED04]

    • Discussion on wire structures

  • [C.W. Fok, Int’l Journal of High Speed Elec. & Sys 02]

    • Discussion on error due to ignoring on-chip inductance

    • Effect of on-chip inductance becomes significant when package impedance is small.


Contribution of this work

Contribution of this work

  • Experimental studies

    • To evaluate effect of on-chip inductance under various power consumption distribution

    • To reveal that decap. position is important to mitigate on-chip inductance effect as well as to suppress power noise

    • To study robustness of power grid with respect to grid pitch, wire area and PG spacing


Power grid structure

Power grid structure

  • Power and ground wires are routed in pairs.

  • Only topmost power/ground grid is considered.

  • Bumps are uniformly attached at some of crossing points.


Equivalent circuit model

Power IO

Cell parasitic capacitance

and well capacitance

Load current source that

models switching gates

Equivalent circuit model


Experimental setup single current source

Experimental setup(single current source)

  • A single current source excited

    • All NAND2 gates in 3,000mm2 switch

    • Tr: 50, 66, 100ps (constant power dissipation)

  • P/G wire: 10mm wide, 1mm thick, 100mm pitch

  • 130nm technology, supply voltage 1.2V

  • 2x2mm2 chip, 9+9 bumps for P/G

  • Each bump 0.5nH, 1W

  • Full PEEC model: all mutual inductances considered.

  • Half area is occupied by NAND2 gates


Difference between w and w o on chip inductance

1.215

1.21

Without on-chip

inductance

1.205

1.2

1.195

With on-chip inductance

Tr = 100ps

1.19

With on-chip inductance

Tr = 66ps

1.185

With on-chip inductance

Tr = 50ps

1.18

0

50

100

150

200

250

Time [ps]

Difference between w/ and w/o on-chip inductance

  • Big difference between w/ and w/o on-chip inductance

  • Without on-chip inductance, not strong dependence on Tr.

With on-chip L,

quadratic

dependence on Tr


Decap size position and noise amplitude

Decap size, position and noise amplitude

  • Decap 100mm far hardly works.

  • Decap at current source works well.

Decap position is important for noise suppression

when on-chip inductance is significant.


Experimental setup realistic power consumption

Experimental setup(realistic power consumption)

  • 0.13mm technology, 1.2V supply voltage

  • Chip size 6x6mm2,100+100 bumps for P/G

  • Each bump 0.5nH, 1W

  • PG wires: pitch 300mm, width 30mm, thickness 1mm

  • Full PEEC model: all mutual inductances considered

  • Half area is occupied by NAND2 gates

  • Power consumption models

    • Uniform: 20% of transistors switching uniformly

    • Unbalance: 50% of transistors switching at center, and 10% at periphery. Total power consumption is the same with uniform case

    • Current transition time Tr: 50ps


Power consumption distribution and power noise

Power consumption distribution and power noise

Uniform power dissipation

Unbalance power dissipation

on-chip L effect small

on-chip L effect significant


Why on chip l hardly affects voltage fluctuation

When load currents are the same or

enough decap is available at each grid,

current flowing through branch is very small.

These inductances hardly affect voltage fluctuation.

Why on-chip L hardly affects voltage fluctuation


Decap placement and power noise

Decap placement and power noise

Adaptive decap placement

Uniform decap placement

work well

on-chip L effect small when decap is enough

not work efficiently

on-chip L effect large


Comparison between peec and decoupled models

Comparison between PEEC and decoupled models

When paired PG wires are

coupled perfectly,

self-inductance L-M,

mutual-inductance 0

(decoupled model)

Difference exists, yet not significant.

Decoupled model is used for larger grid analysis.


Grid pitch and power noise

310

300

290

280

Noise voltage [mV]

270

260

250

240

50

100

150

200

250

300

Grid pitch [um]

Grid pitch and power noise

Wire area is fixed to 20%.

Noise voltage is reduced as grid pitch decreases.


Wire area and power noise

Wire area and power noise

  • Wire area increase reduces noise, yet not drastically.

  • Finer grid is more efficient than large wire area.

10% reduction

7% reduction

Grid pitch 300mm

Grid pitch 50mm


Conclusion

Conclusion

  • Evaluated effects of on-chip inductance

    • Decap position is important

    • Non-uniform power consumption distribution increases effects of on-chip L

    • Adaptive decap insertion based on local power consumption mitigates on-chip L effects

    • Grid pitch is more important than wire area for improving power grid robustness.


  • Login