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Silicon VLSI Technology Fundamentals, Practice and Modeling by J. D. Plummer, M. D. Deal, and P. B. Griffin PowerPoint PPT Presentation


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Silicon VLSI Technology Fundamentals, Practice and Modeling by J. D. Plummer, M. D. Deal, and P. B. Griffin. Chapter 1 Introduction to Technology and Devices. ECE 6466 “ IC Engineering ” Dr. Wanda Wosik. UH; F2013. Chapter 1: INTRODUCTION.

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Silicon VLSI Technology Fundamentals, Practice and Modeling by J. D. Plummer, M. D. Deal, and P. B. Griffin

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Silicon vlsi technology fundamentals practice and modeling by j d plummer m d deal and p b griffin l.jpg

Silicon VLSI TechnologyFundamentals, Practice and Modelingby J. D. Plummer, M. D. Deal, and P. B. Griffin

Chapter 1

Introduction to Technology and Devices

ECE 6466 “IC Engineering”

Dr. Wanda Wosik

UH; F2013


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Chapter 1: INTRODUCTION

• This course is basically about silicon chip fabrication, the technologies used to

manufacture ICs.

• We will place a special emphasis on computer simulation tools to help

understand these processes and as design tools.

• These simulation tools are more sophisticated in some technology areas than in

others, but in all areas they have made tremendous progress in recent years.

• 1960 and 1990 integrated circuits.

• Progress due to: Feature size reduction - 0.7X/3 years (Moore’s Law).

Increasing chip size - ≈ 16% per year.

“Creativity” in implementing functions.


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Evolution of the Silicon Integrated Circuits since 1960s

Increasing: circuit complexity, packing density, chip size, speed, and reliability

Decreasing: feature size, price per bit, power (delay) product

1960s

1990s


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G. Marcyk


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Device Scaling Over Time

~13% decrease in feature size each year (now: ~10%)

Era of Simple Scaling

Cell dimensions

~16% increase in complexity each year (now:6.3% for µP, 12% for DRAM)

Scaling + Innovation

(ITRS)

0.25µm in 1997

Invention

Atomic dimensions

• The era of “easy” scaling is over. We are now in a period where

technology and device innovations are required. Beyond 2020, new

currently unknown inventions will be required.


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ITRS.net


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ITRS.net


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ITRS.net


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2004

2010

2013

2016

1999

2001

2007

1997

2 nodes

G. Marcyk, Intel


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Trends in ScalingSi Microeletronics and MEMS


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Trends in Increasing Integration Scale of CircuitsPast, Present, and Future ICs

ITRS at http://public.itrs.net/ (2003 version + 2004 update) – on class website.

• Assumes CMOS technology dominates over entire roadmap.

• 2 year cycle moving to 3 years (scaling + innovation now required).

• 1990 IBM demo of Å scale “lithography”.

• Technology appears to be capable of making structures much smaller than

currently known device limits.


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Historical Perspective

• Invention of the bipolar

transistor - 1947, Bell Labs.

• Shockley’s “creative failure”

methodology

• Grown junction transistor

technology of the 1950s


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Building Blocks of Integrated Circuits

Bipolar Transistors(BJT) and Metal Oxide Semiconductor Field Effect Transistors (MOSFET) with n- and p-type channels.

• Alloy junction technology of the 1950s.

Fabrication of Bipolar Transistors in the 1950s

Ge used as a crystal, III and V group atoms used as dopants

3rd group

Al wires

p-n-p transistor

Exposed junctions had degraded surface properties and no possibility of connecting multiple devices


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Evolution of the Fabrication Process

The Mesa Design of Bipolar Transistors

Bell Lab, 1957, Double Diffused Process

Contacts alloyed

Solid state B diffusion

Mesa etched

Solid state P diffusion

Advantage: Connection of multiple devices but no ICs

Disadvantage: Degradation by exposed junctions at the surface


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• The planar process (Hoerni -

Fairchild, late 1950s).

• First “passivated” junctions.

• Basic lithography process

which is central to today’s

chip fabrication.


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Evolution of the Fabrication Process: The Planar Design of Bipolar Transistors

Beginning of the Silicon Technology and the End of Ge devices

Implementation of a masking oxide to protect junctions at the Si surface

Oxidation possible for Si not good for Ge

Lithography to open window in SiO2

Boron diffusion

SiO2

Mask

Phosphorus diffusion through the oxide mask

Oxidation and outdiffusion

The planar process of Hoerni and Fairchild (1950s)


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Beginning of Integrated Circuits in 1959

Kilby (TI) and Noyce (Fairchild Semiconductors)

Photolithography used for Pattern Formation

  • Sensitive to light

  • Durable in etching

• Basic lithography process

which is central to today’s

chip fabrication.


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Alignment of Layers to Fabricate IC Elements

  • • Lithographic process allows integration of multiple devices side by side on a wafer.

  • Bipolar Transistor and resistors made in the base region

  • Accuracy of placement ~1/4 to 1/3 of the linewidth being printed

BJT

B

0V

Vcc

C

E

Resistor

Base

R=L/W•Rs

Resistor

Emitter

Contact to collector

Collector


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Schematic Cross-Section of Modern CMOS Integrated Circuit with Two Metal Levels

IC is located at the surface of a Si wafer (~500µm thick)

Interconnect

M2

OXIDE

Via

M1

Silicide

TiN

Oxide Isolation

NMOS

PMOS


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Modern IC with a Five Level Metallization Scheme.

Planarization


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• Actual cross-section of a modern

microprocessor chip. Note the

multiple levels of metal and

planarization. (Intel website).

Computer Simulation Tools (TCAD)

•Most of the basic technologies in silicon chip manufacturing can now be simulated.

Simulation is now used for:

• Designing new processes and devices.

• Exploring the limits of semiconductor devices and technology (R&D).

• “Centering” manufacturing processes.

• Solving manufacturing problems (what-if?)


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• Simulation of an

advanced local

oxidation process.

• Simulation of

photoresist exposure.


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