Address decoding for memory and i o
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Address Decoding for Memory and I/O. Address Decoding. Address Decoding Designs Full Address Decoding Partial Address Decoding Block Address Decoding Implementation Random, Decoders, PROM, FPGA. Address Decoding. Required for a microcomputer where memory and I/O support are essential

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Address Decoding for Memory and I/O

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Address decoding for memory and i o

Address Decoding for Memory and I/O

Lecture 3 - Instruction Set - Al


Address decoding

Address Decoding

  • Address Decoding Designs

    • Full Address Decoding

    • Partial Address Decoding

    • Block Address Decoding

  • Implementation

    • Random, Decoders, PROM, FPGA

Lecture 3 - Instruction Set - Al


Address decoding1

Address Decoding

  • Required for a microcomputer where memory and I/O support are essential

  • Needed for embedded system when on chip microcontroller memory is not sufficient

Lecture 3 - Instruction Set - Al


The memory space

The Memory Space

  • 2 basic approaches

    • Memory mapped system – main memory and I/O space are just different addresses or regions – or memory mapped I/O (MMIO)

      • Addressing is the same pins for memory and I/O

      • Advantage – less pin and hardware complexity

    • Port Mapped I/O – have unique pins (signals) that differentiate memory and I/O address spaces

      • Advantage – If limited memory, memory is memory

      • Advantage – Large I/O space

Lecture 3 - Instruction Set - Al


Other architectures

Other architectures

  • Harvard Architecture

    • Separate memory spaces for instructions and data

    • Requires pin(s) to differentiate

    • I/O is MMIO

  • Check these out on www.wikipedia.com

Lecture 3 - Instruction Set - Al


The 68000 memory space

The 68000 Memory Space

  • 23 address lines

    • 223 words with UDS* and LDS*

  • This is 8M words or 16M bytes

Lecture 3 - Instruction Set - Al


Address map

Address Map

  • When implementing a system the designer creates a memory map.

  • Map would include where RAM, ROM and I/O are.

Lecture 3 - Instruction Set - Al


Full address decoding

Full address decoding

  • Each addressable location within the memory components responds to only a single unique address.

Lecture 3 - Instruction Set - Al


Example of full address decoding

Example of full address decoding

Lecture 3 - Instruction Set - Al


Ex continued

Ex continued

Lecture 3 - Instruction Set - Al


Partial address decoding

Partial Address Decoding

  • Some of address lines are unused

  • Least complex and most inexpensive

  • Each component will actually respond to several addresses

Lecture 3 - Instruction Set - Al


Partial address decoding example

Partial Address decoding example

Lecture 3 - Instruction Set - Al


Block address decoding

Block Address decoding

  • Compromise between full and partial.

  • Don’t decode all of address lines but do decode more than the bare minimum.

  • Less repeated addresses for each populated device

Lecture 3 - Instruction Set - Al


Designing the decode logic

Designing the decode logic

  • Multiple methods of implementing the decode logic

  • One method is of course to implement it with “random logic” – i.e., AND gates, OR gates, inverters, NAND gates, NOR gates

  • Advantage – speed

  • Disadvantage – possibly the number of chips

Lecture 3 - Instruction Set - Al


Decoders

Decoders

  • USE m-line-to-n-line decoders

  • Decode an m-bit input into one of n outputs where n = 2m

  • Popular 74LS138 – 3-to-8 decoder

  • Another 74LS154 – 4-to-16 decoder

Lecture 3 - Instruction Set - Al


Decoder truth table

Decoder Truth table

Lecture 3 - Instruction Set - Al


Example of decoder use

Example of decoder use

Lecture 3 - Instruction Set - Al


Implementation

Implementation

Lecture 3 - Instruction Set - Al


Proms

PROMS

  • A PROM can also be use to implement logic functions

  • Can use it to do address decoding

Lecture 3 - Instruction Set - Al


Example of prom use

Example of PROM use

  • Decoder design must be cheap and versitle.

Lecture 3 - Instruction Set - Al


Prom programming

PROM Programming

Lecture 3 - Instruction Set - Al


Prom system

PROM System

  • Advantage-

    • Ability to select blocks of differing size

    • Versitility

Lecture 3 - Instruction Set - Al


Fpga pla pal

FPGA, PLA, PAL

  • Programmable Logic Arrays

    • AND plane – OR plane

  • Programmable Array Logic

    • Limited PLA

  • FPGA – A network of CLBs

Lecture 3 - Instruction Set - Al


Pal vs pla

PAL vs PLA

  • In a PAL the ouput’s connection to product terms is fixed

  • More limited logic equation support

Lecture 3 - Instruction Set - Al


Special devices

Special devices

  • There are also special chips specifically designed for address decoding

  • Some may be designed for a specific family of chips

Lecture 3 - Instruction Set - Al


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