Processor Architecture
Download
1 / 26

David O’Hallaron - PowerPoint PPT Presentation


  • 79 Views
  • Uploaded on

Processor Architecture Logic Design. David O’Hallaron. Carnegie Mellon University. http:// mprc.pku.edu.cn / ics /. Overview of Logic Design. Fundamental Hardware Requirements Communication How to get values from one place to another Computation Storage Bits are Our Friends

loader
I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
capcha
Download Presentation

PowerPoint Slideshow about ' David O’Hallaron' - hanh


An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript

Processor Architecture

Logic Design

David O’Hallaron

Carnegie Mellon University

http://mprc.pku.edu.cn/ics/


Overview of logic design
Overview of Logic Design

  • Fundamental Hardware Requirements

    • Communication

      • How to get values from one place to another

    • Computation

    • Storage

  • Bits are Our Friends

    • Everything expressed in terms of values 0 and 1

    • Communication

      • Low or high voltage on wire

    • Computation

      • Compute Boolean functions

    • Storage

      • Store bits of information


Digital signals

0

1

0

Voltage

Time

Digital Signals

  • Use voltage thresholds to extract discrete values from continuous signal

  • Simplest version: 1-bit signal

    • Either high range (1) or low range (0)

    • With guard range between them

  • Not strongly affected by noise or low quality circuit elements

    • Can make circuits simple, small, and fast


Computing with logic gates

a && b

Computing with Logic Gates

  • Outputs are Boolean functions of inputs

  • Respond continuously to changes in inputs

    • With some, small delay

Falling Delay

Rising Delay

b

Voltage

a

Time


Combinational circuits

Acyclic Network

Primary

Inputs

Primary

Outputs

Combinational Circuits

  • Acyclic Network of Logic Gates

    • Continously responds to changes on primary inputs

    • Primary outputs become (after some delay) Boolean functions of primary inputs


Bit equality

Bit equal

a

eq

b

Bit Equality

  • Generate 1 if a and b are equal

  • Hardware Control Language (HCL)

    • Very simple hardware description language

      • Boolean operations have syntax similar to C logical operations

    • We’ll use it to describe control logic for processors

  • HCL Expression

    bool eq = (a&&b)||(!a&&!b)


    Word equality

    b31

    Bit equal

    eq31

    a31

    b30

    Bit equal

    eq30

    a30

    Eq

    B

    =

    Eq

    b1

    Bit equal

    eq1

    A

    a1

    b0

    Bit equal

    eq0

    a0

    Word Equality

    Word-Level Representation

    • 32-bit word size

    • HCL representation

      • Equality operation

      • Generates Boolean value

    HCL Representation

    bool Eq = (A == B)


    Bit level multiplexor
    Bit-Level Multiplexor

    • Control signal s

    • Data signals a and b

    • Output a when s=1, b when s=0

    s

    Bit MUX

    HCL Expression

    bool out = (s&&a)||(!s&&b)

    b

    out

    a


    Word multiplexor

    s

    b31

    out31

    a31

    s

    b30

    out30

    MUX

    B

    Out

    a30

    A

    b0

    out0

    a0

    Word Multiplexor

    Word-Level Representation

    • Select input word A or B depending on control signal s

    • HCL representation

      • Case expression

      • Series of test : value pairs

      • Output value for first successful test

    HCL Representation

    int Out = [

    s : A;

    1 : B;

    ];


    Hcl word level examples

    MIN3

    C

    Min3

    B

    A

    s1

    s0

    MUX4

    D0

    D1

    Out4

    D2

    D3

    HCL Word-Level Examples

    Minimum of 3 Words

    • Find minimum of three input words

    • HCL case expression

    • Final case guarantees match

    int Min3 = [

    A < B && A < C : A;

    B < A && B < C : B;

    1 : C;

    ];

    4-Way Multiplexor

    • Select one of 4 inputs based on two control bits

    • HCL case expression

    • Simplify tests by assuming sequential matching

    int Out4 = [

    !s1&&!s0: D0;

    !s1 : D1;

    !s0 : D2;

    1 : D3;

    ];


    Arithmetic logic unit

    2

    1

    0

    3

    Y

    Y

    Y

    Y

    A

    A

    A

    A

    X ^ Y

    X & Y

    X + Y

    X - Y

    X

    X

    X

    X

    B

    B

    B

    B

    OF

    OF

    OF

    OF

    ZF

    ZF

    ZF

    ZF

    CF

    CF

    CF

    CF

    A

    L

    U

    A

    L

    U

    A

    L

    U

    A

    L

    U

    Arithmetic Logic Unit

    • Combinational logic

      • Continuously responding to inputs

    • Control signal selects function computed

      • Corresponding to 4 arithmetic/logical operations in Y86

    • Also computes values for condition codes


    Storing 1 bit

    V2

    q

    Q+

    !q

    Q–

    Vin

    V1

    q = 0 or 1

    Storing 1 Bit

    Bistable Element


    Storing 1 bit cont

    V2

    q

    Q+

    !q

    Q–

    Vin

    V1

    Stable 1

    q = 0 or 1

    Vin = V2

    V2

    Vin

    V1

    Metastable

    Stable 0

    Storing 1 Bit (cont.)

    Bistable Element


    Physical analogy

    Stable 1

    .

    .

    .

    Metastable

    Stable 0

    Physical Analogy

    Metastable

    Stable left

    Stable right


    Storing and accessing 1 bit

    Bistable Element

    R-S Latch

    q

    Q+

    R

    Q+

    !q

    Q–

    Q–

    q = 0 or 1

    S

    Resetting

    Setting

    Storing

    1

    0

    0

    1

    0

    !q

    0

    1

    q

    1

    0

    !q

    0

    1

    q

    0

    1

    0

    Storing and Accessing 1 Bit


    1 bit latch

    D

    R

    Q+

    Q–

    C

    S

    Latching

    Storing

    d

    !d

    !d

    !d

    d

    d

    !d

    0

    !q

    q

    1

    0

    !q

    q

    d

    d

    !d

    0

    1-Bit Latch

    D Latch

    Data

    Clock


    Transparent 1 bit latch

    Changing D

    Time

    Latching

    C

    d

    !d

    !d

    !d

    d

    D

    Q+

    1

    d

    d

    !d

    Transparent 1-Bit Latch

    • When in latching mode, combinational propogation from D to Q+ and Q–

    • Value latched depends on value of D as C falls


    Edge triggered latch

    C

    T

    D

    Q+

    Time

    Edge-Triggered Latch

    • Only in latching mode for brief period

      • Rising clock edge

    • Value latched depends on data as clock rises

    • Output remains stable at all other times

    D

    R

    Data

    Q+

    Q–

    C

    S

    T

    Clock

    Trigger


    Registers

    i7

    D

    o7

    Q+

    C

    i6

    D

    o6

    Q+

    C

    i5

    D

    o5

    Q+

    C

    i4

    D

    o4

    Q+

    I

    O

    C

    i3

    D

    o3

    Q+

    C

    i2

    D

    o2

    Q+

    C

    i1

    Clock

    D

    o1

    Q+

    C

    i0

    D

    o0

    Q+

    C

    Clock

    Registers

    Structure

    • Stores word of data

      • Different from program registers seen in assembly code

    • Collection of edge-triggered latches

    • Loads input on rising edge of clock


    Register operation

    Rising

    clock

    State = y

    y

    Output = y

    Register Operation

    • Stores data bits

    • For most of time acts as barrier between input and output

    • As clock rises, loads input

    State = x

    x

    Input = y

    Output = x


    State machine example

    Comb. Logic

    0

    MUX

    0

    Out

    In

    1

    Load

    Clock

    Clock

    Load

    A

    L

    U

    x0

    x1

    x2

    x3

    x4

    x5

    In

    x0

    x0+x1

    x0+x1+x2

    x3

    x3+x4

    x3+x4+x5

    Out

    State Machine Example

    • Accumulator circuit

    • Load or accumulate on each cycle


    Random access memory

    valA

    Register

    file

    srcA

    A

    valW

    Read ports

    W

    dstW

    Write port

    valB

    srcB

    B

    Clock

    Random-Access Memory

    • Stores multiple words of memory

      • Address input specifies which word to read or write

    • Register file

      • Holds values of program registers

      • %eax, %esp, etc.

      • Register identifier serves as address

        • ID 15 (0xF) implies no read or write performed

    • Multiple Ports

      • Can read and/or write multiple words in one cycle

        • Each has separate address and data input/output


    Register file timing

    Register

    file

    Register

    file

    y

    2

    valW

    valW

    W

    W

    dstW

    dstW

    x

    valA

    Register

    file

    srcA

    A

    2

    Clock

    Clock

    valB

    srcB

    B

    x

    2

    Rising

    clock

    y

    2

    Register File Timing

    • Reading

      • Like combinational logic

      • Output data generated based on input address

        • After some delay

    • Writing

      • Like register

      • Update only as clock rises

    x

    2


    Hardware control language
    Hardware Control Language

    • Very simple hardware description language

    • Can only express limited aspects of hardware operation

      • Parts we want to explore and modify

  • Data Types

    • bool: Boolean

      • a, b, c, …

    • int: words

      • A, B, C, …

      • Does not specify word size---bytes, 32-bit words, …

  • Statements

    • bool a = bool-expr ;

    • int A = int-expr ;


  • Hcl operations
    HCL Operations

    • Classify by type of value returned

  • Boolean Expressions

    • Logic Operations

      • a && b, a || b, !a

    • Word Comparisons

      • A == B, A != B, A < B, A <= B, A >= B, A > B

    • Set Membership

      • A in { B, C, D }

        • Same as A == B || A == C || A == D

  • Word Expressions

    • Case expressions

      • [ a : A; b : B; c : C ]

      • Evaluate test expressions a, b, c, … in sequence

      • Return word expression A, B, C, … for first successful test


  • Summary
    Summary

    • Computation

      • Performed by combinational logic

      • Computes Boolean functions

      • Continuously reacts to input changes

    • Storage

      • Registers

        • Hold single words

        • Loaded as clock rises

      • Random-access memories

        • Hold multiple words

        • Possible multiple read or write ports

        • Read word when address input changes

        • Write word as clock rises


    ad