Logic Synthesis EEG 707 Dr Henry Selvaraj Department of Electrical and Computer Engineering

1. Logic Synthesis EEG 707 Dr Henry Selvaraj Department of Electrical and Computer Engineering University of Nevada, Las Vegas

2. Our Communication Room TBE B324 702 - 895 - 4184 selvaraj@ee.unlv.edu

3. MW: between 12:00 and 2:00 p.m. Office Hours You may also call me and fix an appointment for any other suitable time.

4. Subject Homepage The subject homepage is located at: http://www.ee.unlv.edu/~selvaraj/eeg707 • Important announcements and notices will be posted in this page. You may also find some support materials for this subject.

5. Semester Grades will be computed as follows: 2 exams 225 points (100+125) final exam/project 150 points home work/projects 125 points ____________ Total 500 points

6. Design Methodologies The implementation of a digital system depends on the design style. Constraints: size and role, economics and etc.

7. ICs consist of transistors that are placed on the chip and are connected in such a way to realize the design. The locations and connectivity of the transistors are defined by severalmasks. A mask corresponds to one of the silicon compound layers that form the transistors and the interconnect layers.

8. Design methodology Semicustom Full Custom Standard Cells Gate Arrays Programmable Logic FPGAs PLDs Design Methodologies

9. Application Specific Integrated Circuits (ASICs) can be defined as ICs designed for a particular application in low volumes or end use. Semicustom or standard ICs are field programmable (eg. Microprocessors)

10. Custom ICs Custom ICs are created using unique masks for all layers during the manufacturing process. The user controls chip density with high utilization. Designer controls all stages of the chip layout and maximum design flexibility and high performance are possible. Only highly trained engineers are engaged in design. Developmental time is long and costs are extremely high. The high cost of design and testing can be successfully amortized over the high volume.

11. Field Programmable Devices Like gate arrays, field programmable devices are prefabricated. However, the logic is implemented by electrically programming the interconnects and personalizing the basic cells, typically at the user’s place.

12. Programmable Logic Devices (PLDs) PLDs consist of programmable AND arrays and programmable OR gates that are followed by flip-flops. Initially, PLDs used to be fabricated with bipolar technology; however, complementary metal-oxide semiconductors (CMOSs) are more popular now.

14. Field Programmable Gate Array (FPGA) FPGAs combine the architecture of gate arrays with programmability of PLDs. Some of the FPGA real estate is occupied by vendor logic to implement the field programmability feature of the FPGA, and a large portion of the die is for programmable routing.

15. The logic block (known also as LC, CLB and etc.) consists of some universal gates, that is gates that can be programmed to represent any function. The connectivity between blocks is programmed via different types of devices, SRAM (static random-access memory), EEPROM, or antifuse.

16. Two basic architectures: Matrix based: CLBs form islands in a matrix with horizontal and vertical channels. Eg.: Xilinx and QuickLogic CLBs form rows separated by routing channels like in a mask-programmable gate array. Eg.: Actel

17. Advantages of of FPGAs Replacement of SSI and MSI chips (eg. A circuit with 250 TTL7400 SSI chips (1000 NAND gates) can be replaced by a Xilinx3000 series chip.) Availability of parts off the shelf rapid turnaround low risk reprogrammability

18. Limitation of FPGAs - your opportunities The FPGA -based circuit delay depends on the performance of the design implementation tools. The mapping of the logic design into the FPGA’s architecture requires sophisticated design implementation (CAD) tools.

19. 1. entering the design in the form of schematic, netlist, logic expressions or hardware description languages 2. simulating the design for functional verification 3. mapping the design into the FPGA architecture 4. placing and routing the FPGA design The Design cycle

20. 5. extracting delay parameters of the routed design 6. resimulating for timing verification 7. generating the FPGA device configuration format 8. configuring or programming the device 9. testing the product for undesirable functional behavior

21. For every FPFA, the vendor provides design implementation tools to perform steps 3 through 8. Steps 1 and 2 can be performed using simulation software like PALASM, ABEL or VHDL editors/simulators.

22. Synthesis Simply put, synthesis is the translation of a design representation to a form that is amendable to minimal realization. High level synthesis: eg. VHDL to RTL Logic Synthesis: RTL-gate-level representation

23. Factors that can influence the design: architacture gate density routing resources programming method

24. Truth tables The example describes a 2-output / 4-input binary valued logic function. The input-names are in1, input, carry and enable, and the output- names are out1 and y2 respectively. The truth-table specifies the ON-set and the DC-set of the function as set by the type-command. The truth-table itself describes the function by means of three lines, using lots of don't cares. # this is a comment line, I love comments ;-) .type fd .i 4 .o 2 .ilb in1 input carry enable .ob out1 y2 0000 11 0001 1- 1--- -1 .e

25. Basic commands Command Parameter Description .type type Specifies the interpretation of the contents of the truth-table. The following types are possible: f, r, fd, fr, dr, fdr. .i n Specifies the number (n) of input variables. .o n Specifies the number (n) of output variables. .ilb in1 in2 ... Specifies the names of the binary valued input variables. .ob on1 on2 ... Specifies the names of the binary valued output variables. .e Specifies the end of the PLA-file.

26. Truth-table types Type Meaning f The truth-table specifies only the ON-set of the function. The OFF-set is calculated automatically. Therefore the function is completely specified (a boolean function), because the DC-set is empty. r The truth-table specifies only the OFF-set of the function. The ON-set is calculated automatically. Therefore the function is completely specified (a boolean function), because the DC-set is empty. fd The truth-table specifies the ON-set and the DC-set of the function. The OFF-set ist calculated automatically. dr The truth-table specifies the DC-set and the OFF-set of the function. The ON-set is calculated automatically. fr The truth-table specifies the ON-set and the OFF-set of the function. The DC-set is calculated automatically. fdr The truth-table specifies the ON-set, the OFF-set and the DC-set of the function.

27. Truth-table Input Output Description 0-01 1- The left field specifies an input condition (number of bits must match the .i n command). The right field specifies the corresponding function output (number of bits must match the .o n command). 0 denotes logical 0, 1 denotes logical 1 and - denotes a don't care, both in the input- and in the output-field. In the output-field a don't care can also be denoted by a ~, which means in the PLA, that the corresponding input term (product) is not connected in the sum of the output.