Controllers system for aps cubesat nano satellite
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Technion – Israel Institute of Technology Department of Electrical Engineering High Speed Digital Systems Lab. Controllers-system for APS – CubeSat nano-satellite. Presentation Part A. Instructor: Daniel Alkalay Students: Moshe Emmer & Meir Harar. Agenda. Project Goals

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Controllers system for aps cubesat nano satellite

Technion – Israel Institute of Technology

Department of Electrical Engineering

High Speed Digital Systems Lab

Controllers-system for APS – CubeSatnano-satellite

Presentation Part A

Instructor: Daniel Alkalay

Students: Moshe Emmer & Meir Harar


Agenda

Agenda

  • Project Goals

  • Architecture/Interface

  • Progress So Far

    • Re-Defining part A goal

    • Implementation

    • Further achievements

  • What next..

  • Schedule


  • Project goals

    Project Goals

    • APS – Cubesat is a Multidisciplinary project . It involves AE and EE disciplines.

    • AE provide: Mission design, Orbital design, Systems architecture, Attitude control, choosing sensors, actuators and Mechanical design.

    • AE will provide System design and algorithms. Our goal is to implement OBC (On Board Controllers) - H/W and S/W. Algorithms implemented include: Attitude-control, power management, Telemetry and RF communications systems.


    Cubesat architecture interface

    שעון

    אטומי

    Accurate

    Positioning

    System

    Magneto-meter

    מד שמש

    Rate Gyro

    APS & TLM

    TransCeiver

    מגנטו-טורקרים

    Engines

    Power

    CubeSat - Architecture / Interface

    Control

    Payload

    Power

    Distribution

    Over-current

    control

    Telemetry

    Battery

    SA I/F &

    Bat C/D-

    Control

    TLM

    TLM

    On-Board

    Controllers

    uBlaze +

    pBlaze +

    State-Machines

    TLM

    TT+C

    Attitude System Sensors & actuators

    S

    &

    A

    I

    /

    F

    Sensors

    Attitude

    Control

    Actuators


    Progress so far

    Progress So Far

    Re-Defining part A goal -

    • Create a design, using MicroBlaze soft processor, that will implement a communication protocol between O.B.C and external host PC (Using Hyper terminal).

    • The design will be divided into two parts:

    • Hardware – building system architecture using available busses, peripherals IP’s etc’

    • Software – implementing a small C program and translate it into MicroBlaze target using EDK and available IP’s


    Progress so far implementation

    Progress So Far - Implementation

    • Using MicroBlaze Processor on Spartan 3 board

    • Defining a task – Calculator, operated by an external User

    • Defining and exploring I/O method – UartLite.


    Uart lite

    UART Lite

    • A module that attaches to the OPB.

    • One transmit and one receive channel (full duplex).

    • 16-character transmit FIFO and 16-character receive FIFO.

    • Configurable baud rate.

    • Parameters:


    Progress so far hardware

    Progress So Far - Hardware

    Microblaze_0

    Peripherals – OPB IP’s

    UARTRS -232

    DIP_Switches_8Bit

    OPB

    OPB

    … …

    LEDs_8Bit

    I-LMB

    D-LMB

    Push_Buttons_3Bit

    I-LMB Cntrl

    BRAM_0

    D-LMB Cntrl

    Led_7SEGMENT

    L.M.B – Local Memory Bus

    Tested and studied, not included in design

    Tested and studied - included in design


    Progress so far software

    Progress So Far - Software

    • Locating and exploring building blocks for the design (Functions)

    • Creating headers files, in which all relevant functions defined

    • Implementing a main.c code, executing a calculator Task.

    Out of calc.c

    Out of main.c

    static void DisplayAnswer(int Answer)

    {

    Xboolean Negative = XFALSE;

    /*

    * If a negative answer, send the absolute value

    * the LEDs

    */

    if (Answer < 0)

    {

    Negative = XTRUE;

    Answer = Answer * (-1); /* abs value of negative */

    }

    XGpio_mSetDataReg(LEDS_BASEADDR, 1, Answer);

    DisplaySegments(Answer, Negative);

    case '+':

    Answer=Operand1+Operand2;

    break;

    case '-':

    Answer=Operand1-Operand2;

    break;

    case '*':

    Answer=Operand1*Operand2;

    break;

    default:

    printf("Error\n");

    break;


    Progress so far architecture

    Progress So Far - Architecture

    • Studying and exploring new techniques in order to enable a simultaneous 2-task execution (using two microprocessors).

    • Learning and adopting the usage of Fast Simplex Link, a shared bus for two different microprocessors.

    • Embracing a new board, Virtex-II-Pro, ML310 and implementing a design that includes all.


    Progress so far the new ml310 board

    Progress So Far - The new ML310 board

    ALi SB

    PCISlots

    Virtex-II Pro

    Parallel, Serial, USB & Ethernet ports

    DDR DIMM


    Progress so far ml310 peripherals

    Progress So Far - ML310 peripherals

    • LCD

    • Connected directly to the FPGA

    • Can be operated using the PowerPC (C/C++) only.

    • Useful functions :

      • LCDInit: Initialize the LCD before it can be operated.

      • LCDWrite: Write data to the LCD.

      • LCDCls: Clear the LCD Screen.

    • LEDS

    • Can be operated using both the PowerPC (C/C++) or the FPGA alone (VHDL/VERILOG)

    • Useful Commands in EDK :

      • XGpio_mSetDataDirection(BaseAddress,1,0x00000000);Set the I/O device with BaseAddress as output (0).

      • XGpio_mSetDataReg(BaseAddress, 1, data);Write data to the I/O device with BaseAddress.


    Controllers system for aps cubesat nano satellite

    Progress So Far - FSL (Fast Simplex Link) Bus

    A uni-directional point-to-point FIFO-based communication


    Controllers system for aps cubesat nano satellite

    Progress So Far - FSL (Fast Simplex Link) Bus

    Microblaze_0

    Microblaze_1


    Progress so far fsl fast simplex link bus

    Progress So Far - FSL (Fast Simplex Link) Bus

    We used this bus to transfer data between two soft processors implemented on the same chip

    Technical Features

    • Up to 8 master and slave FSL interfaces are available on the MicroBlaze soft processor.

    • Supports both synchronous and asynchronous FIFO modes – allows the master and slave side of the FSL to clock at different rates.

    • Provides an external control bit for annotating data being transmitted – can be used by the slave side interface for multiple purposes. For example, use the bit to indicate the start or end of the transmission of a frame.

    Master_a

    Slave_b

    FSL_a

    Microblaze_0

    Microblaze_1

    FSL_b

    Slave_a

    Master_b


    Schedule

    Convert AE’s C code to fixed-point and integrate it into our system. (2 weeks)

    Ramp-up on Virtex-IV. (1 weeks)

    FSM – study and implement (temperature sensors management). (2 weeks)

    CubeSat architecture – definition & specifications. (1-2 weeks)

    Implement AE’s algorithms into our architecture – convergence. (4 weeks)

    Schedule


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