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Power-Aware and BIST-Aware NoC Reuse on the Testing of Core-based Systems

Power-Aware and BIST-Aware NoC Reuse on the Testing of Core-based Systems. Érika Cota Luigi Carro Flávio Wagner Marcelo Lubaszewski UFRGS Porto Alegre, Brazil. Context. SoC. core. core. core. core. core. core. Reuse Model. tester. SoC. core. core. core. core.

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Power-Aware and BIST-Aware NoC Reuse on the Testing of Core-based Systems

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  1. Power-Aware and BIST-Aware NoC Reuse on the Testing of Core-based Systems Érika Cota Luigi Carro Flávio Wagner Marcelo Lubaszewski UFRGS Porto Alegre, Brazil

  2. Context SoC core core core core core core

  3. Reuse Model tester SoC core core core core core core

  4. Reuse Model tester SoC core core core core core core

  5. Reuse Model tester SoC core core core core core core

  6. Revisão dos principais objetivose fatores de sucesso Goal Improve the reuse the on-chip network as test access mechanism • minimal area overhead • zero pin overhead • feasible test time Power consumption is an issue? Optimal set of BISTed cores?

  7. Revisão dos principais objetivose fatores de sucesso Outline • NoC-based Test • Power consumption calculation • Modified scheduling • Considering BISTed cores • Experimental Results • Final Remarks

  8. Access Paths Within the NoC input CUT 1 input CUT 2 output output

  9. CUT CUT CUT 2 Access Paths Within the NoC input CUT 1

  10. CUT CUT Access Paths Within the NoC CUT 1 input CUT 2

  11. CUT CUT CUT 2 Access Paths Within the NoC CUT 1 output

  12. CUT CUT Access Paths Within the NoC CUT 1 CUT 2 output

  13. CUT CUT Access Paths Within the NoC input CUT 1 CUT 2

  14. CUT CUT Access Paths Within the NoC input CUT 1 CUT 2

  15. CUT CUT Access Paths Within the NoC CUT 1 CUT 2 output

  16. CUT CUT Access Paths Within the NoC CUT 1 CUT 2 output

  17. Parallelism Within the NoC input input CUT 1 CUT 2 output output

  18. Pipeline Within the NoC input input CUT 1 CUT 2 output CUT 3 output

  19. Pipeline Within the NoC input input CUT 1 CUT 2 output CUT 3 output

  20. Pipeline Within the NoC input input CUT 1 CUT 2 output CUT 3 output

  21. Pipeline Within the NoC BOTTLENECKS! input CUT 1 CUT 2 CUT 3 output

  22. Packets Scheduling input CUT 1 CUT 2 output CUT 3

  23. Packets Scheduling input CUT 1 CUT 2 output CUT 3

  24. Packets Scheduling input CUT 1 CUT 2 output CUT 3

  25. Packets Scheduling input CUT 1 CUT 2 output CUT 3

  26. Packets Scheduling input CUT 1 CUT 2 output CUT 3

  27. Reuse Algorithm Define test packets Define access paths for each core Select a packet Find available access path Schedule packet

  28. wrapper wrapper wrapper wrapper Power Consumption Calculation Core 1 Core 2 Core 3 wrapper wrapper Router Router Router Core 4 Core 5 Core 6 Router Router Router

  29. wrapper wrapper wrapper wrapper Power Consumption Calculation Core 1 Core 2 Core 3 wrapper wrapper Router Router Router Core 4 Core 5 Core 6 Router Router Router

  30. wrapper wrapper wrapper wrapper Power Consumption Calculation • F(#ffs, #gates, switching rate) • per cycle (any frequency) • per packet Core 1 Core 2 Core 3 wrapper wrapper Router Router Router Core 4 Core 5 Core 6 Router Router Router

  31. wrapper wrapper wrapper wrapper Power Consumption Calculation • F(length,width,switching rate) • per cycle (any frequency) Core 1 Core 2 Core 3 wrapper wrapper Router Router Router Core 4 Core 5 Core 6 Router Router Router

  32. wrapper wrapper wrapper wrapper Power Consumption Calculation • F(#ffs, #gates, switching rate) • per cycle (any frequency) • per pattern Core 1 Core 2 Core 3 wrapper wrapper Router Router Router Core 4 Core 5 Core 6 Router Router Router

  33. CUT Power Consumption of One Packet input CUT 1 CUT 4*PW(router) + 3*PW(channel) + PW(CUT+wrapper)

  34. Power-Aware Scheduling

  35. Power-Aware Scheduling

  36. Power-Aware Scheduling

  37. Experimental Setup • SOCIN Network • under development at UFRGS • Grid topology • 32-bit channels • deterministic routing (XY) • ITC’02 SoC Test Benchmarks • d695, g1023 • Placement for synthetic applications

  38. Experimental Results - d695 Cores consumption >> wrapper consumption Test time Power Limit

  39. Experimental Results - g1023 Cores consumption >> wrapper consumption

  40. Experimental Results - d695 Cores consumption  wrapper consumption Test time Power Limit

  41. Experimental Results - g1023 Cores consumption  wrapper consumption

  42. BIST-Aware Scheduling • Each core has a BISTed version • 30% more area • 50% more power consumption • 2x the number of test vectors • All cores BISTed • system test time = largest test time among cores • power consumption may be na issue

  43. BIST-Aware Scheduling 1) All cores BISTed • maximum parallelization • minimum test time? 2) Define test scheduling considering power constraints 3) Replace the core with largest test time by its external tested version 4) Repeat 2 and 3 until test time increases

  44. Experimental Results - p22810 No power constraints BISTed Cores

  45. Experimental Results - p22810 No power constraints BISTed Cores

  46. Experimental Results - p22810 No power constraints BISTed Cores

  47. Experimental Results - p22810 Multiple BIST model BISTed Cores

  48. Final Remarks • Alternative TAM for NoC-based SoCs • good trade-off test time x area X pin overhead even under power constraints (ETW’03) • Selection of the optimal set of BISTed cores for test time minimization (TRP’03) • Further selection of the best BIST method for the cores in the system

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