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CERN Electronics Pool. Tools for Discovery. Digital Pulse Processing Workshop June 23 rd 2010, CERN Carlo Tintori. Outline. Description of the hardware of the waveform digitizers Use of the digitizers for physics applications

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CERN

Electronics Pool

Tools for Discovery

Digital Pulse Processing Workshop

June 23rd 2010, CERN

Carlo Tintori


Outline

  • Description of the hardware of the waveform digitizers

  • Use of the digitizers for physics applications

  • Comparison between the traditional analog acquisition chains and the new fully digital approach

  • DPP algorithms:

    • Pulse triggering

    • Zero suppression

    • Pulse Height Analysis

    • Charge Integration

    • Time measurement

    • Gamma-Neutron discrimination

    • Multi Channel Scaler

  • Overview on the CAEN Digitizer family

  • Experimental setup description and practical demonstrations

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited


Digitizers vs Oscilloscopes

  • The principle of operation of a waveform digitizer is the same as the digital oscilloscope: when the trigger occurs, a certain number of samples (acquisition window) is saved into one memory buffer

  • However, there are important differences:

    • no dead-time between triggers (Multi Event Memory)

    • multi-board synchronization for system scalability

    • high bandwidth data readout links

    • on-line data processing (FPGA or DSP)

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited


Block Diagram

  • Mother-daughter board configuration:

  • The mother board defines the form-factor; it contains one FPGA for the readout interfaces and the services (power supplies, clocks, I/Os, etc…)

  • The daughter board defines the type of digitizer; it contains the input amplifiers, the ADCs, the FPGA for the data processing and the memories


Board Layout

Opt. Link

TRG in-out

CLK in-out

DAC out

I/Os

ADC

PLL

FPGA

FPGA

Lin. Reg.

LOCAL BUS

DC-DC

DC-DC

Memory

VME

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Multi board synchronization i
Multi-board synchronization (I)

  • Clock distribution

    • External Clock In/Out (differential LVDS)

    • Clock Distribution:

      • Daisy Chain: Clock-Out to Clock-In chain (the first board can act as a clock master)

      • Fan-Out: one clock source + 1 to N fan-out

    • High performance and low jitter PLL for clock synthesis

      • Frequency multiplication: necessary when the sampling clock frequency is high

      • Jitter cleaning: the PLL can reduce the jitter coming from the external clock source

    • Programmable clock phase adjust to compensate the cable delay

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Multi-board synchronization (II)

  • Trigger and Sync Distribution

    • External Trigger In/Out

    • Trigger Time Stamp synchronous with the ADC sampling clock

    • External Sync input to start-stop the acquisition synchronously and/or to keep the time stamp alignment between boards

    • External Trigger and Sync must be synchronous with the sampling clock

    • The trigger re-synchronization causes a jitter of one clock period (trigger uncertainty)

    • It is necessary to digitize the trigger signal in the cases where the trigger is used as a time reference to be correlated with the channels

    • The trigger latency can be compensated by means of the pre-trigger size (memory look back)

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Triggers and acquisition

  • Trigger types:

    • External Trigger (same as the ‘Ext Trigger’ in the scopes)

    • Software Trigger (same as the ‘Auto Trigger’ in the scopes)

    • Self-Trigger (same as the ‘Normal Trigger’ in the scopes)

  • The trigger can be common to all the channels in a board (like in the scopes) or individual; in the first case, the self trigger of one channel is propagated to the others

  • Self trigger: just a simple threshold or advanced triggers based on digital algorithms implemented in the FPGAs (input pulse recognition)

  • Programmable Acquisition Window and Pre/Post Trigger Size

  • Dead-Timeless Multi Event Acquisition (memory paging)

  • Some digitizers have auxiliary digital I/Os or communication busses that allow to use external trigger logics (coincidences, multiplicity, etc…)

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Fundamentals of A/D conversion

  • Analog Bandwidth <= Sampling rate / 2

  • LSB = Dynamic Range / 2Nbit

  • Quantization noise:  = LSB / 12 = ~ 0.3 LSB

  • SNR = 20 log (S/N); THD = 20 log (S/D); SINAD = 20 log (S / (N+D))

  • Effective Number of bits: ENOB = (SINAD – 1.76dB) / 6.02

  • Oversampling: Fovs = 4 Nadd* Fs  N’bit = Nbit + NAdd

  • Sampling clock jitter: SNRJITTER = -20 log (2 FANALOG TJITTER)

  • Other sources of noise: DNL, INL

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Digitizers for Physics Applications

  • Traditionally, the acquisition chains for radiation detectors are made out of mainly analog circuits; the A to D conversion is performed at the very end of the chain

  • Nowadays, the availability of very fast and high precision flash ADCs permits to design acquisition systems in which the A to D conversion occurs as close as possible to the detector

  • In theory, this is an ideal acquisition system (information lossless)

  • The data throughput is extremely high: it is no possible to transfer row data to the computers and make the analysis off-line!

  • On-line digital data processing in needed to extract only the information of interest (Zero Suppression & Digital Pulse Processing)

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Traditional chain example 1 charge sensitive preamplifiers
Traditional chain: example 1charge sensitive preamplifiers

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Traditional chain: example 1trans-impedance (current sensitive) preamplifier

  • The QDC is not self-triggering; need a gate generator

  • need delay lines to compensate the delay of the gate logic

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Benefits of the digital approach

  • One single board can do the job of several analog modules

  • Full information preserved

  • Reduction in size, cabling, power consumption and cost per channel

  • High reliability and reproducibility

  • Flexibility (different digital algorithms can be designed and loaded at any time into the same hardware)

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Readout Bandwidth

  • Example with Mod720:

    • 1 sample = 12 bit = 1.5 byte

    • 1 channel = 1.5 byte @ 250MHz = 375 MB/s

    • 1 VME board = 8 channels = 3 GB/s !!!

  • Continuous acquisition not possible!

  • Example2 (triggered acquisition):

    • Record length = 512 samples (~ 2 s) = 768 bytes per channel

    • Trigger Rate = 10 KHz

    • 1 VME board = ~ 61 MB/s

  • Readout Bandwidth of CAEN digitizers:

    • VME with MBLT: 60 MB/s

    • VME with 2eSST: 150 MB/s

    • Optical Link: 70 MB/s

    • USB 2.0: 30 MB/s

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Digital pulse detection self triggering
Digital Pulse detection (self-triggering)

  • A good trigger is the basis for both the DPP and the Zero Suppression

  • The aim of the self-trigger is to identify the good pulses and trigger the acquisition on channel by channel basis

  • Pulse identification can be difficult because of the noise, baseline fluctuation, pile-up, fast repetition, etc…

  • Trigger algorithms based on a fixed voltage threshold are not suitable for most physics applications

  • It is necessary to apply digital filters able to reject the noise, cancel the baseline and to do shape and timing analysis

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Dpp algorithms for triggering
DPP algorithms for triggering

  • Timing filter RC-(CR)N issues:

    • High frequency noise rejection (RC filter  mean)

    • Baseline restoration (CR or CR2 filter  1st or 2nd derivative)

    • Immune to pile-up and low frequency noise (baseline fluctuation)

    • Bipolar signal  Zero crossing time-stamp (digital CFD)

  • Constraints on the Time Over Threshold and/or zero crossing can be added to improve the noise rejection

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Dpp for the zero suppression
DPP for the Zero Suppression

  • Data reduction algorithms can be developed to reduce the data throughput:

    • Full event suppression: one event (acquisition window) is discarded if no pulse is detected inside the window

    • Zero Length Encoding: only the parts exceeding the threshold (plus a certain number of samples before and after) are saved.

ZLE

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Dpp for the pulse height analysis dpp tf
DPP for the Pulse Height Analysis (DPP-TF)

  • Digital implementation of the shaping amplifier + peak sensing ADC (Multi-Channel Analyzer)

  • Implemented in the 14 bit, 100MSps digitizers (mod. 724)

  • Use of trapezoidal filters to shape the long tail exponential pulses

  • Pile-up rejection, Baseline restoration, ballistic deficit correction

  • High counting rate, very low dead time

  • Energy and timing information can be combined

  • Best suited for high resolution spectroscopy (especially Germanium detectors)

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Dpp tf block diagram
DPP-TF Block Diagram

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Dpp tf analog chain set ups
DPP-TF / Analog Chain set-ups

N1470High Voltage

N968

Shaping

Amplifier

N957

Peak

Sensing ADC

Energy

60Co137Cs

C.S. PRE

Ge / Si

DT5724

14bit @ 100MSps

Digitizer + DPP-TF

Energy

Time

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Dpp tf vs analog chain
DPP-TF vs Analog Chain

  • PROs

    • All in one board

    • Stability and reproducibility

    • Counting rate (lower dead-time)

    • Source Activity measurement (count all pulses)

    • Ballistic deficit correction

    • Timing information

    • Dynamic Range

    • Channel density

    • Synchronization and coincidences in multiple channel systems

    • Total Cost per Channel

    • Better Energy Resolution (?)

  • CONs

    • Parameters set-up (need good software interface)

    • Getting started more difficult

    • Lower Energy Resolution (?)

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Dpp tf test results
DPP-TF: Test Results

  • Tested with Germanium Detectors at LNL (Legnaro - Italy) in Nov-08 and Feb-09, at GSI (Germany) on May-09, at INFN-MI on Jan-10, in Japan on Feb-10: resolution = 2.2 KeV @ 1.33 MeV (60Co)

  • Tested with Silicon Strip (SSSSD and DSSSD) and CsI detectors in Sweden at Lund and Uppsala (ion beam test)

  • Tested with NaI detectors in CAEN (see demo)

  • Tested with PET in U.S.A.

  • Tested for a homeland security application using CsI

60Co with

Ge

228Th with

DSSSD

FWHM @ 1.33 MeV:

2.2 KeV

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Dpp for the charge integration dpp ci
DPP for the Charge Integration(DPP_CI)

  • Digital implementation of the QDC + discriminator and gate generator

  • Implemented in the 12 bit, high speed digitizers ( Mod. 720(*) )

  • Self-gating integration; no delay line to fit the pulse within the gate

  • Automatic pedestal subtraction

  • Extremely high dynamic range

  • Dead-timeless acquisition (no conversion time)

  • Energy and timing information can be combined

  • Typically used for PMT or SiPM/MPPC readout and for gamma-neutron discrimination in scintillating detectors

(*) Implementation in the Mod751 is being studied

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Dpp ci block diagram
DPP-CI Block Diagram

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Dpp ci analog chain set ups
DPP-CI / Analog Chain set-ups

N1470High Voltage

DelayN108A

QDCV792N

Charge

Splitter

A315

CFDN842

Dual TimerN93B

PMT

NaI(Tl)

60Co137Cs

TDC V1190

Time

DT5720

12bit @ 250MSps

Digitizer + DPP-CI

Charge

Time

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Dpp ci vs analog chain
DPP-CI vs Analog Chain

  • PROs

    • All in one board

    • Stability and reproducibility

    • Self-Independent-Retroactive-Adaptive Gate

    • No conversion time (dead-timeless acquisition)

    • Baseline restoration

    • Accept positive, negative and bipolar signals

    • Extremely wide Dynamic Range

    • Coincidences between couples of channels

    • Total Cost per Channel

    • Better Energy/Timing Resolution (?)

  • CONs

    • Parameters set-up (need good software interface)

    • Getting started more difficult

    • Channel density

    • Lower Energy/Timing Resolution (?)

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Dpp ci test results
DPP-CI: Test Results

Resolution = FWHM * 100 / Mean

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Dpp ci other tests
DPP-CI: Other Tests

  • Tested with SiPM/MPPC detectors at Univerità dell’Insubria (Como – Italy) and in CAEN (2009/2010):

    • Dark Counting Rate

    • LED pulser

    • Readout of a 3x3mm Lyso Crystal + Gamma source

    • Readout of a scintillator tile for beta particles

  • 0.5 ph

  • 1.5 ph

  • 2.5 ph

  • Threshold scan

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Dpp for time measurements
DPP for Time Measurements

  • Digital implementation of the TDC + CFD

  • Actually implemented in both DPP-TF and DPP-CI (without interpolation)

  • Digital algorithms to implement Constant Fraction Discriminators or Timing Filters (RC-CRN)

  • Extremely high dynamic range

  • Dead-timeless acquisition (no conversion time)

  • Interpolation between a set of samples can increase the resolution well beyond the sampling period (up to picoseconds)

  • Resolution strongly dependent on pulse signal rise-time and amplitude (V/ T)

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Digital algorithms for timing analysis
Digital algorithms for Timing Analysis

  • Positive/negative pulses digitally transformed into bipolar pulses

  • The Zero Crossing doesn’t depend on the pulse amplitude

  • Timing filters: RCN or Digital CFD

  • Optional RC filter (mean filter) to reduce the HF noise

  • ZC interpolations:

    • Linear (2 points)

    • Cubic (4 points)

    • Best fit line or curve (4 or more points)

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Digital CFD and Timing Filters

NOTE: the higher ZC slope and the lower tail, the better filter

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ZC timing errors

  • The timing resolution is affected by three main sources of noise:

    • Electronic noise in the analog signal (not considered here)

    • Quantization error Eq

    • Interpolation error Ei

  • Both simulations and experimental test demonstrate that there are two different regions:

  • When Rise Time > 5*Ts the pulse edge can be well approximated to a straight line, hence Ei is negligible. The resolution is proportional to the rise time and to the number of bits of the ADC.

  • When Rise Time < 5*Ts the approximation to a straight line is too rough and Ei is the dominant source of error. The resolution is still proportional to the number of bit but becomes inversely proportional to the rise time. Resolution improvement expected for cubic interpolation.

  • The best resolution is for Rise Time = 5*Ts, regardless the type of digitizer

  • The resolution is always proportional to the pulse amplitude (more precisely to the slope V/T)

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Sampling Clock phase effect (RT<5Ts) (I)

DELAYAB = N * Ts:

same clock phase for A and B 

same interpolation error 

ERRA  ERRB 

Error cancellation in calculating TIMEAB

TIMEAB = (ZCA + ERRA) – (ZCB + ERRB) = ZCA– ZCB + (ERRA- ERRB )

DELAYAB = (N+0.5) * Ts:

rotated clock phase for A and B 

same interpolation error 

ERRA  ERRB 

No error cancellation. ERRA and ERRB are symmetric: twin peak distribution

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Sampling Clock phase effect (RT<5Ts) (II)

DELAY = N * Ts

DELAY = (N + 0.5) * Ts

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Sampling Clock phase effect (RT<5Ts) (III)

Vpp = 100mV

Rise Time = Ts

Emulation

14bit – 100MSps

12bit – 250MSps

10bit – 1GSps

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Sampling Clock phase effect (RT<5Ts) (IV)

Vpp = 100mV

Mod720: 12bit 250MSps

Emulation

5 ns

10 ns

Rise Time

15 ns

20 ns

30 ns

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Preliminary results: Mod724

(14 bit, 100 MS/s)

DELAYAB = (N+0.5) * Ts (worst case)

50 mV

StdDev (ns)

100 mV

200 mV

500 mV

RiseTime (ns)

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Preliminary results: Mod720

(12 bit, 250 MS/s)

DELAYAB = (N+0.5) * Ts (worst case)

50mV

100mV

200mV

StdDev (ns)

500mV

RiseTime (ns)

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Preliminary results: Mod751

(10 bit, 1 GS/s)

DELAYAB = (N+0.5) * Ts (worst case)

50mV

100mV

200mV

StdDev (ns)

500mV

NOTE: the region with Rise Time < 5*Ts (5 ns) is missing in this plot

RiseTime (ns)

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Mod724 vs Mod720 vs Mod751

Amplitude = 100 mV

10 bit, 1 GS/s

12 bit, 250 MS/s

14 bit, 100 MS/s

StdDev (ns)

RiseTime (ns)

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Mod751 @ 2 GS/s

The cubic interpolation can reduce the gap between best and worst case as well as increase the resolution for small signals!

StdDev (ns)

RT = 1 ns - worst case

RT = 5 ns

RT = 1 ns - best case

  2 ps !

Amplitude (mV)

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Dpp for n discrimination
DPP for -n Discrimination

  • Digital implementation of the double gate QDC or rise time discriminator

  • Different digital algorithms

    • rise-time/energy correlation (charge sensitive preamplifiers)

    • double gate charge integration (PMTs or current sensitive preamplifiers)

    • zero crossing

  • It’s a combination of the previous energy and timing DPP algorithms

  • Dead-timeless acquisition (no conversion time)

  • Algorithms being tested (collaboration with Duke University)

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N discrimination block diagram
-n Discrimination Block Diagram

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Dpp for pulse counting sca
DPP for Pulse Counting (SCA)

  • Digital implementation of the discriminator + scaler (Single-Channel Analyzer)

  • Can be implemented in the high density digitizers (mod. 740)

  • Pulse Triggering: baseline restoration, noise rejection, etc…

  • Single or Multi-Channel Energy Windowing

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Dpp readout modes
DPP readout modes

Waveform mode

  • same operating mode of the standard firmware (except for the individual pulse triggering)

  • The memory buffer contains one acquisition window (1 trigger  1 buffer)

  • Very useful during the parameters setting and debug

  • High data throughput  low counting rate (typ. < 1KHz)

  • The waveform mode allows the users to develop and test new DPP algorithms (off-line analysis)

    List mode

  • Readout of lists of events

  • 1 event = Energy (Charge/Height), Time Stamp, samples for ZC interpolation

  • The memory buffer contains many events (N triggers  1 buffer)

  • Small data size  high counting rate (1 MHz or more)

  • Histograms, coincidences, etc… easily implemented off line

    Mixed Mode

  • Energy and/or Time stamps saved within the waveform samples

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Building dpp algorithms
Building DPP algorithms

  • The digitizer is a general purpose acquisition module; in most cases it requires a dedicated firmware or software to implement a specific application

  • The first algorithm validation can be done using software signal emulators (mathlab, LabView, C/C++, etc…). Everything happens inside the computer

  • Then it is then possible to verify the algorithm applying them to real data read from the digitizer in oscilloscope mode (off-line)

  • Once validated, the algorithm must be implemented in the FPGA (VHDL or Verilog) or DSP (C/C++) of the digitizer

  • Finally, the algorithm can be tested on-line

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Caen waveform digitizers
CAEN Waveform Digitizers

  • VME, NIM, PCI Express and Desktop

  • VME64X, Optical Link (CONET), USB 2.0, PCI Express Interfaces available

  • Memory buffer: up to 10MB/ch (max. 1024 events)

  • Multi-board synchronization and trigger distribution

  • Programmable PLL for clock synthesis

  • Programmable digital I/Os

  • Analog output with majority or linear sum

  • FPGA firmware for Digital Pulse Processing

    • Zero Suppression

    • Pulse Triggering

    • Trapezoidal Filters for energy calculation

    • Digital CFD for timing information

    • Digital Charge Integration

    • Pulse Shape Analysis

    • Coincidence

    • Possibility of customization

  • Software Tools for Windows and Linux

  • From 2 to 64 channels

  • Up to 5 GS/s sampling rate - Up to 14 bit

  • FPGA firmware for Digital Pulse Processing

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Digitizers table
Digitizers Table

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Mod724: 14 bit, 100 MS/s

  • Very high resolution and low noise digitizer

  • DPP-TF for Pulse Height Analysis (Trapezoidal Filters)

  • Replacement of the shaping amplifier + peak sensing ADC

  • Three dynamic range options (500mVpp, 2.25Vpp and 10Vpp)

  • Best suited for very accurate energy measurements

  • Good timing resolution with slow signals (rise time >= 50 ns)

  • Mid-Low speed signals (Typ: output of charge sensitive preamplifiers)

  • Applications:

    • Spectroscopy (MCA) with Ge, Si and other detectors

    • Any application using charge sensitive pre-amplifiers

    • Low noise applications

    • Neutrino and dark matter physics

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Mod720: 12 bit, 250 MS/s

  • Best compromise between resolution and speed

  • DPP-CI for Charge Integration

  • Best suited for PMT and SiPM/MPPC readout

  • Mid-High speed signals (Typ: output of PMT/SiPM)

  • Good timing resolution with fast signals (rise time < 100 ns)

  • Applications:

    • Spectroscopy with NaI, CsI and other detectors (fast pre-ampli)

    • Gamma Neutron discrimination

    • Single Photon Counting

    • PET

    • Homeland Security

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Mod740: 12 bit, 65 MS/s

  • High channel density

  • No DPP available (few FPGA resources)

  • Best suited for high density systems

  • Low speed signals (Typ: output of sensors, CCDs or shaping amplifiers)

  • Applications:

    • Sensors readout (temperature, pressure, CCD, etc…)

    • Coincidence Matrix

    • Imaging

    • Single channel analyser

    • Readout of Shaping Amplifiers

    • TPC readout systems

    • Any application with many channels

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Mod751/761: 10 bit, 1-2-4 GS/s

  • Very high sampling rate

  • 2 GS/s: half channels; 4GS/s: one fourth channels

  • No DPP available (DPP-CI perhaps available in the future)

  • Best suited for very high speed detectors (diamond? LaBr? …)

  • High speed signals (Typ: output of wideband amplifiers)

  • Applications:

    • Diamond detectors

    • RPC readout systems

    • Time of flight

    • Fast PMT readout

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Mod721/731: 8bit, 0.5-1 GS/s

  • Precursor of the od751; today its low cost version

  • No DPP available

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Mod742: 12bit, 5 GS/s

  • Excellent combination of very high sampling rate, resolution and high density

  • Based on the DRS chip (developed by S. Ritt at PSI)

  • No DPP available (at least for the moment)

  • Best suited for very high energy and timing resolution applications

  • Very high speed / high dynamics signals

  • Mixed fast and slow acquisition mode

  • 50-100us Dead Time: not suitable for high counting rate

  • Max. 1024 points: not suitable for long pulses

  • Applications:

    • Fast detector test benches

    • Cherenkov Telescopes

    • Ultra precise Pulse Shape discrimination

    • Very high resolution TDC (5-10 ps)?

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited


Experimental demo 1
Experimental Demo 1

VME

V1718

VME-USB

Bridge

USB

V6534High Voltage

USB

60Co

850V

DT5724

14bit @ 100MS/s

Digitizer + DPP-TF

Energy

Charge Sensitive

Preamplifier for PMT

NaI(Tl)

PMT

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited


Experimental demo 2
Experimental Demo 2

VME

V1718

VME-USB

Bridge

USB

V6534High Voltage

60Co

-650V

V1720

12bit @ 250MS/s

Digitizer + DPP-CI

Charge

LaBr3

PMT

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited


Experimental demo 3
Experimental Demo 3

VME

V1718

VME-USB

Bridge

USB

Trigger

V1720

12bit @ 250MS/s

Digitizer + DPP-CI

Charge

LED

PULSER

SP5600

USB

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited


Experimental demo 4
Experimental Demo 4

VME

USB

V6534High Voltage

USB

450V

A1422

Charge Sensitive

Preamplifier

DT5724

14bit @ 100MS/s

Digitizer + DPP-TF

Energy

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited


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