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Cryo and AFE IIt Update. MICE Collaboration Meeting October 22, 2005 RAL A. Bross. Cryo Update I. The cryo-system for the VLPCs has been operated extremely reliably and stably from May through the end of the KEK TB However, it was felt that the thermal-link design could be made more robust

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cryo and afe iit update

Cryo and AFE IIt Update

MICE Collaboration Meeting

October 22, 2005

RAL

A. Bross

cryo update i
Cryo Update I
  • The cryo-system for the VLPCs has been operated extremely reliably and stably from May through the end of the KEK TB
  • However, it was felt that the thermal-link design could be made more robust
    • A bolted concept has now been detailed and will be used in all subsequent systems
  • The drawing package has been “marked-up” for update
  • The drawing package is currently in the Fermilab drafting queue.
  • There are a few outstanding issues that still need some thought
    • Is the top plate stiff enough against atmospheric pressure?
    • Can the new thermal link design permit non-positive clamping of the cassette so that a cassette could be removed from the cryostat without having to break the cryo-vacuum
afe iit update
AFE IIt Update
  • The AFE IIt prototypes (10) have arrived and are under test
  • The production run of Tript chips is complete, and approximately 8200 die have been packaged.
    • Enough for about 500 boards
afe iit test status
AFE IIt test Status
  • The AFE IIt board test is making very good progress
    • All power applied (AFEI power supply values)
    • 1553 communications functional
    • JTAG programming chain working
    • RT1553 FPGA operating properly
    • PIC microcontroller operating properly using new C code (at least for those tests we have performed so far)
    • HELPER FPGA operating properly for the functions we have checked so far
    • CLOCKGEN FPGA operating properly, clocks being generated, phase control from the PC, through 1553 is working properly.
    • Program and read the FLASH memory
    • Use the FLASH to program the DFPGAs
    • Use the FLASH to program the AFPGAs
    • ADC for measuring bias and temp is working
    • Bias DACs, heater DACs are working
  • Next Steps
    • Test the slow communications to AFPGAs and DFPGAs
    • Apply power to TriP-t chips and ADCs
    • Run the TriP-t and ADCs through the ACQUIRE/DIGITIZE/READOUT cycle
  • Lots of FPGA programming to Do!
tript
TriPt
  • We now have all the packaged TriPts that will be needed
  • Preliminary testing:
    • Linearity problem at small charge input has indeed been fixed
tript ii
TriPt II
  • Bandwidth performance looks good
tript iii
TriPt III
  • Discriminator Performance as expected
    • Likely not an issue with MICE
tript iv
TriPt IV
  • TDC Gain has large spread
    • This was expected and can be taken out (calibration) off-line
tript v
TriPt V
  • Time-walk as expected.
issues that will need some thought
Issues that will Need some Thought
  • AFE IIt board temperature and bias calibration
    • Does MICE need a test stand (like D0 has) to do this operation?
  • LED pulser data
    • Plan to dismount wavguides and mount a LED pulser or excite the fibers with blue LEDs?
  • New LVSB Board
  • AVNET (timing) board incorporated into LVSB or possibly the AFE IIt can be programmed to take over the functionality of the AVNET board
  • Rate
    • If we keep analog and timing information we are limited to:
      • 1/(150 X 19 ns) @350 muons per msec of spill
        • It is possible that clever (extreme) programming of the AFE IIt can push this up a bit – 400-450 or so.
    • If we drop analog and timing and only use discriminators, we can run at 7 MHz.
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