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IceCube DAQ PowerPoint PPT Presentation

IceCube Design Requirements IceCube DAQ Reliability, Quality Assurance Lessons Learned Performance

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IceCube DAQ

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Overview l.jpg

Overview

  • IceCube

  • Design Requirements

  • IceCube DAQ

  • Reliability, Quality Assurance

  • Lessons Learned

  • Performance

IceCube DAQ Design and Performance

Thorsten Stezelberger


Icecube l.jpg

IceCube

  • 70-80 Strings

  • 60 DOMs per String

  • IceTop Air Shower Array on top of String

IceCube DAQ Design and Performance

Thorsten Stezelberger


Design requirements l.jpg

Design Requirements

  • 10-15 Years lifetime goal

  • Reliability / Robust Design

  • Remotely controllable

  • Failure must not propagate

  • Resistant to Radio Frequency Interference

  • Expected Hit rate ~0.8 kHz

  • Low power consumption < 5W/DOM

  • Surface temperatures -20°C to -70°C

  • At-depth temperatures -10°C to -40°C

IceCube DAQ Design and Performance

Thorsten Stezelberger


Physics requirements l.jpg

Physics Requirements

  • Timing, 7ns RMS4ns RMS

  • Waveform capture

    300MS/s for 400ns, 40MS/s for 6.4µs

  • Charge Dynamic Range

    >200PE/15ns~500PE/15ns

  • In Situ Calibration (internal and external)

  • In-Ice Hardware Local Coincidence

IceCube DAQ Design and Performance

Thorsten Stezelberger


Daq system overview l.jpg

DAQ System Overview

Ethernet

DAQ

E

l

e

c

t

r

o

n

i

c

s

IceCube DAQ Design and Performance

Thorsten Stezelberger


Timedomains l.jpg

GPS

Master Clock

SP (String Processor)

Hub

DOM: “local time units”

Hub: “ master time units”

SP: transforms local time stamps to master time

DOMs (60/string)

Timedomains

IceCube DAQ Design and Performance

Thorsten Stezelberger


Domhub l.jpg

DOMHub

DOM Power Supplies

Power Distr. Card

Chassis Fans

Hard Drive

CPU

8 DOR Cards

GPS

distr.

IceCube DAQ Design and Performance

Thorsten Stezelberger


Do m r eadout card l.jpg

DOM Readout Card

DOM Communication DOM Power Input GPS Master Time Input

Main Cable Connector PCI interface DOM Power Distribution

IceCube DAQ Design and Performance

Thorsten Stezelberger


Main cable l.jpg

Main Cable

  • 0.9mm Twisted Quad Copper Cable

  • 2.5km long (continuous in ice) + Surface Cable

  • 2 DOMs per wire pair

  • Power, Timing and Communications over the same wire pair

  • > 50dB suppression near end cross talk

  • > 30 db suppression far end cross talk

IceCube DAQ Design and Performance

Thorsten Stezelberger


Digital optical module l.jpg

Digital Optical Module

Passive Base

HV Supply

Flasher Board

Main Board

Delay Board

IceCube DAQ Design and Performance

Thorsten Stezelberger


Dom main board l.jpg

DOM Main Board

IceCube DAQ Design and Performance

Thorsten Stezelberger


Dom main board13 l.jpg

Trigger (2)

10b

FPGA

ADC

Pulser

1

megabaud

and

DOR

x16

8b

Delay

1

5

DAC

LPF

10b

SOPC

ATWD

4

8

x2

+/

-

5V, 3.3V,

DC

-

DC

x0.25

10b

2.5V, 1.8V

ATWD

x 9

x 2.6

Configuration

10b

CPU

8Mbit

fADC

Device

MUX

DP

40 MHz

32b

OB

-

LED

Ram

SDRAM

16Mb

(n+1)

16Mb

LC

SDRAM

(n

1)

20 MHz

Flash

Flash

16b

Monitor

CPLD

Oscillator

4Mb 4Mb

& Control

Corning Frequency

Ctl

Flasher

(was Toyocom)

8b

DACs & ADCs

64 Bytes

PMT Power

Board

8b, 10b, 12b

DOM Main Board

IceCube DAQ Design and Performance

Thorsten Stezelberger


Dom main board14 l.jpg

Trigger (2)

10b

FPGA

ADC

Pulser

1

megabaud

and

DOR

x16

8b

Delay

1

5

DAC

LPF

10b

SOPC

ATWD

4

8

x2

+/

-

5V, 3.3V,

DC

-

DC

x0.25

10b

2.5V, 1.8V

ATWD

x 9

x 2.6

Configuration

10b

CPU

8Mbit

fADC

Device

MUX

DP

40 MHz

32b

OB

-

LED

Ram

SDRAM

16Mb

(n+1)

16Mb

LC

SDRAM

(n

1)

20 MHz

Flash

Flash

16b

Monitor

CPLD

Oscillator

4Mb 4Mb

& Control

Corning Frequency

Ctl

Flasher

(was Toyocom)

8b

DACs & ADCs

64 Bytes

PMT Power

Board

8b, 10b, 12b

DOM Main Board

IceCube DAQ Design and Performance

Thorsten Stezelberger


Altera excalibur l.jpg

Altera Excalibur

  • FPGA 400,000 Gates

  • ARM9 CPU

  • Bus bridges between CPU and FPGA

  • Dual Ported Memory between CPU and FPGA

  • Power consumption 0.5 – 0.7W

IceCube DAQ Design and Performance

Thorsten Stezelberger


Dom main board16 l.jpg

Trigger (2)

10b

FPGA

ADC

Pulser

1

megabaud

and

DOR

x16

8b

Delay

1

5

DAC

LPF

10b

SOPC

ATWD

4

8

x2

+/

-

5V, 3.3V,

DC

-

DC

x0.25

10b

2.5V, 1.8V

ATWD

x 9

x 2.6

Configuration

10b

CPU

8Mbit

fADC

Device

MUX

DP

40 MHz

32b

OB

-

LED

Ram

SDRAM

16Mb

(n+1)

16Mb

LC

SDRAM

(n

1)

20 MHz

Flash

Flash

16b

Monitor

CPLD

Oscillator

4Mb 4Mb

& Control

Corning Frequency

Ctl

Flasher

(was Toyocom)

8b

DACs & ADCs

64 Bytes

PMT Power

Board

8b, 10b, 12b

DOM Main Board

IceCube DAQ Design and Performance

Thorsten Stezelberger


Atwd analog transient waveform digitizer l.jpg

ATWDAnalog Transient Waveform Digitizer

  • ASIC

  • Switched Capacitor Array

  • 4 Channels x 128 Samples Deep

  • Sampling on Launch

  • Sample Speed 250 - 800MSamples/s

  • Digitization, ~30µs/waveform

  • Power consumption 125mW

IceCube DAQ Design and Performance

Thorsten Stezelberger


Dom main board18 l.jpg

Trigger (2)

10b

FPGA

ADC

Pulser

1

megabaud

and

DOR

x16

8b

Delay

1

5

DAC

LPF

10b

SOPC

ATWD

4

8

x2

+/

-

5V, 3.3V,

DC

-

DC

x0.25

10b

2.5V, 1.8V

ATWD

x 9

x 2.6

Configuration

10b

CPU

8Mbit

fADC

Device

MUX

DP

40 MHz

32b

OB

-

LED

Ram

SDRAM

16Mb

(n+1)

16Mb

LC

SDRAM

(n

1)

20 MHz

Flash

Flash

16b

Monitor

CPLD

Oscillator

4Mb 4Mb

& Control

Corning Frequency

Ctl

Flasher

(was Toyocom)

8b

DACs & ADCs

64 Bytes

PMT Power

Board

8b, 10b, 12b

DOM Main Board

IceCube DAQ Design and Performance

Thorsten Stezelberger


Oscillator l.jpg

Oscillator

  • Reference “time” of DOM

  • High Reliability Part

  • Screened for short term stability

IceCube DAQ Design and Performance

Thorsten Stezelberger


Dom main board20 l.jpg

Trigger (2)

10b

FPGA

ADC

Pulser

1

megabaud

and

DOR

x16

8b

Delay

1

5

DAC

LPF

10b

SOPC

ATWD

4

8

x2

+/

-

5V, 3.3V,

DC

-

DC

x0.25

10b

2.5V, 1.8V

ATWD

x 9

x 2.6

Configuration

10b

CPU

8Mbit

fADC

Device

MUX

DP

40 MHz

32b

OB

-

LED

Ram

SDRAM

16Mb

(n+1)

16Mb

LC

SDRAM

(n

1)

20 MHz

Flash

Flash

16b

Monitor

CPLD

Oscillator

4Mb 4Mb

& Control

Corning Frequency

Ctl

Flasher

(was Toyocom)

8b

DACs & ADCs

64 Bytes

PMT Power

Board

8b, 10b, 12b

DOM Main Board

IceCube DAQ Design and Performance

Thorsten Stezelberger


Local coincidence l.jpg

Local Coincidence

  • Reduce Data Rate

  • Rate without LC ~1KHz

  • Rate with LC <15Hz

  • Dedicated Full Duplex LC connection

  • Transmit and Receive go through FPGA

  • LC functionality can be reprogrammed

IceCube DAQ Design and Performance

Thorsten Stezelberger


Reliability quality assurance l.jpg

Reliability, Quality Assurance

DOMs are not accessible after deployment

  • By Design

  • Production

  • Testing

IceCube DAQ Design and Performance

Thorsten Stezelberger


Design l.jpg

Design

  • Qualified Manufacturer List

  • GIDEP (Government-Industry Data Exchange Program)

  • No Wet Electrolytic Capacitors

  • Derate Parts

  • HALT (Highly Accelerated Lifetime Testing) Input

  • Serial number; electronic, barcode and human readable

  • Robust Boot Mode

  • Little Redundancy in the DOM (Deployed Spares)

  • MTBF calculation not reliable (Temperature range)

IceCube DAQ Design and Performance

Thorsten Stezelberger


Production l.jpg

Production

  • IPC610 class 3 for Board production and loading

  • No Microwelds in PCB

  • Use of Industrial Temperature Parts

  • Tin-Lead Parts wherever possible (NO pure tin parts)

  • Close work with Board manufacturer and loading house for fast feedback

  • Digital picture of Boards after loading

  • ESD Precautions

IceCube DAQ Design and Performance

Thorsten Stezelberger


Testing l.jpg

Testing

  • Initial room temperature Test

  • HASS (Highly Accelerated Stress Screening)

  • 48 hour Main Board burn-in hot and cold

  • Interface test

  • Integrated DOM burn-in 21 days at various Temp.

  • Test before Deployment at ~-25°C

  • In Summary; Testing, more Testing and even more …

  • All Test results are stored in Database

  • ESD Precautions

IceCube DAQ Design and Performance

Thorsten Stezelberger


Lessons learned l.jpg

Lessons Learned

  • Test Framework (bench, integration, before deployment and after deployment)

  • DOMHub can run standalone

  • Terminal Connection to DOM

  • Script Language/Interpreter on DOM

IceCube DAQ Design and Performance

Thorsten Stezelberger


Performance l.jpg

Performance

One String and 4 IceTop Stations are deployed

  • Time Calibration

  • Noise/Discriminator Threshold

  • Muon Reconstruction

IceCube DAQ Design and Performance

Thorsten Stezelberger


Time calibration reciprocal active pulsing l.jpg

for 76 DOMs

Time CalibrationReciprocal Active Pulsing

Verified using:

  • Flasher Boards

  • IceTop –IceCube coincidences

  • AMANDA – IceCube coincidences

IceCube DAQ Design and Performance

Thorsten Stezelberger


Clock stability l.jpg

Clock Stability

Time Calibration every 3.5s

IceCube DAQ Design and Performance

Thorsten Stezelberger


Noise discriminator threshold l.jpg

Noise/Discriminator Threshold

  • PMT Gain 107

  • Noise in the Ice is ~800Hz

  • Threshold as low as ~1/8SPE

IceCube DAQ Design and Performance

Thorsten Stezelberger


Muon reconstruction l.jpg

Muon Reconstruction

IceCube DAQ Design and Performance

Thorsten Stezelberger


Summary l.jpg

Summary

  • DAQ Design

  • Reliability

  • One IceCube string deployed

  • Four IceTop Stations deployed

  • String is working very well

  • All 76 DOMs function well

  • In Jan, Feb up to 10 more Strings deployed

  • Full Array deployed by 2009-10

IceCube DAQ Design and Performance

Thorsten Stezelberger


Thank you l.jpg

Thank You

IceCube DAQ Design and Performance

Thorsten Stezelberger


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