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CS134a: Memory Management

CS134a: Memory Management. Overall outline Preparing a program for execution Virtual memory, algorithms Shared objects Today Simple memory management Segmentation, paging. Virtual Memory. Hides the features of the real memory from the programmer Provides the illusion that

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CS134a: Memory Management

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  1. CS134a: Memory Management • Overall outline • Preparing a program for execution • Virtual memory, algorithms • Shared objects • Today • Simple memory management • Segmentation, paging Computing Systems Memory management http://mojave.caltech.edu/cs134/a/ October 27, 2014

  2. Virtual Memory • Hides the features of the real memory from the programmer • Provides the illusion that • each process has its own address space, starting at 0 • memory space is (effectively) unlimited • Uses dynamic relocation (implemented in hardware) Computing Systems Memory management http://mojave.caltech.edu/cs134/a/ October 27, 2014

  3. Simple memory management • Scheme 1: fixed partitions • Need a process queue for each partition Computing Systems Memory management http://mojave.caltech.edu/cs134/a/ October 27, 2014

  4. Fragmentation Computing Systems Memory management http://mojave.caltech.edu/cs134/a/ October 27, 2014

  5. Overlays • Large computations may be staged in a series of overlays • Based on call graph Computing Systems Memory management http://mojave.caltech.edu/cs134/a/ October 27, 2014

  6. Problems with simple schemes • Schemes allow • sharing of memory between processes • programs larger than physical space • But memory management is visible to the programmer Computing Systems Memory management http://mojave.caltech.edu/cs134/a/ October 27, 2014

  7. VM Example Computing Systems Memory management http://mojave.caltech.edu/cs134/a/ October 27, 2014

  8. VM outline • Single segment name space • Contiguous allocation • Paging • Multiple-segment name space • Contiguous allocation • Paged segmentation • Hardware for address translation • Page replacement strategies Computing Systems Memory management http://mojave.caltech.edu/cs134/a/ October 27, 2014

  9. VM Implementation issues • Concepts: • A segment is a space corresponding to a logical component (an object, an array, ...) • Physical memory may be divided into pages for memory management purposes • Issues: • Placement: where should virtual memory be loaded into physical memory? • Replacement: what should be removed when there is not enough room for data that is to be loaded? • Load control:when and how much virtual memory should be loaded? Computing Systems Memory management http://mojave.caltech.edu/cs134/a/ October 27, 2014

  10. Process segmentation • Segments are the logical components of the process Computing Systems Memory management http://mojave.caltech.edu/cs134/a/ October 27, 2014

  11. Dynamic address translation Computing Systems Memory management http://mojave.caltech.edu/cs134/a/ October 27, 2014

  12. Single-segment contiguous storage name space • IBM 7090: use a relocation register RR for each virtual space physical_addr Mmap(virtual_addr va) { return va + RR; } • Each process state contains • the program counter p.pc • the base address p.ba of process p’s real memory • Context switch p1 to p2: p1->pc = pc; // save state RR = p1->ba; pc = p1->pc; // load state Computing Systems Memory management http://mojave.caltech.edu/cs134/a/ October 27, 2014

  13. Relocation register, contiguous allocation Computing Systems Memory management http://mojave.caltech.edu/cs134/a/ October 27, 2014

  14. Single register scheme • Relocation register must not be accessible to user-space programs • Programs and data may be swapped in and out easily, since the physical location is not important • Compaction is conceptually easy (although expensive) • Still have external fragmentation • Programs and data are statically linked in virtual memory Computing Systems Memory management http://mojave.caltech.edu/cs134/a/ October 27, 2014

  15. Paging • Divide physical memory into page frames f1,f2,...,fn (typically of size 512-2K words) • An address is a pair (f, w) of a page frame f, and an offset w • Divide virtual memory into pages; address is (p, w) Computing Systems Memory management http://mojave.caltech.edu/cs134/a/ October 27, 2014

  16. Inverted page tables • (Conceptual) relocation register for each frame, stored as a page tablephysical_addr Mmap(p, w) {for(int f = 0; page_table[f] != p; f++);return (i << k) | w; } • ATLAS (Kilburn, 1962) • Provide associative memory in hardware • Defines RR-1 by parallel search in hardware Computing Systems Memory management http://mojave.caltech.edu/cs134/a/ October 27, 2014

  17. Inverse page table Computing Systems Memory management http://mojave.caltech.edu/cs134/a/ October 27, 2014

  18. Associative hardware Computing Systems Memory management http://mojave.caltech.edu/cs134/a/ October 27, 2014

  19. Translating an address II • Each virtual space has its own page table at real address specified in the “page table register” PTR physical_addr Mmap(p, w) { return (Mem[PTR + p] << k) | w; } Computing Systems Memory management http://mojave.caltech.edu/cs134/a/ October 27, 2014

  20. Pentium Paging Computing Systems Memory management http://mojave.caltech.edu/cs134/a/ October 27, 2014

  21. Advantages of paged systems • Placement is simple: any frame may be allocated for any page • Paging partially eliminates external fragmentation (storage lost because a program can’t be loaded) • But it still has internal fragmentation because because the last page is generally only partially filled Computing Systems Memory management http://mojave.caltech.edu/cs134/a/ October 27, 2014

  22. Demand paging • Programs larger than physical memory may be executed with demand paging:physical_addr Mmap(p, w) {if(resident(M[PTR + p]))return (M[PTR + p] << k) | w;raise PageFault; } Computing Systems Memory management http://mojave.caltech.edu/cs134/a/ October 27, 2014

  23. Multiple-segments with contiguous allocation • In this scheme we have only segments (no pages) • Burroughs B5500/B6500 (1964, 1967) • Stack-based machine • segments correspond to procedures, arrays, ADTs, etc • Each virtual space has a segment table stored at address STRphysical_addr Mmap(s, w) {if(resident(M[STR + s]))return M[STR + s] + w;raise SegmentationFault; } Computing Systems Memory management http://mojave.caltech.edu/cs134/a/ October 27, 2014

  24. Pure segmentation Computing Systems Memory management http://mojave.caltech.edu/cs134/a/ October 27, 2014

  25. Pentium Segmentation I Computing Systems Memory management http://mojave.caltech.edu/cs134/a/ October 27, 2014

  26. Pentium Segmentation II Computing Systems Memory management http://mojave.caltech.edu/cs134/a/ October 27, 2014

  27. Contiguous segmentation • Advantages: • segments are variable size • segments preserve the logical structure of the program • Disadvantages: • Complex placement • Demand segmentation requires a complex replacement policy Computing Systems Memory management http://mojave.caltech.edu/cs134/a/ October 27, 2014

  28. Paged segmentation • Try to combine advantages of both • An address is a triple (s, p, w) • Each process has a STR that points to a table of page tables, which in turn point to framesphysical_addr Mmap(s, p, w) {return (M[M[STR + s] + p] << k) + w; } • Typical sizes • GE645: s=18, p=8, w=10 (bits) • IBM 370: s=12, p=8, w=12 • RCA Spectra 70/46: s=5, p=6, w=12 Computing Systems Memory management http://mojave.caltech.edu/cs134/a/ October 27, 2014

  29. Demand loading the page/segment tables • We can make this even more complex! • Address (s1, s2, p, w) • Keep first table in real-space, the rest can be paged physical_addr Mmap(s1, s2, p, w) { return (M[M[M[STR + s1] + s2] + p] << k) | w; } • GE645/MULTICS: s1=8, s2=10, p=8, w=10 bits Computing Systems Memory management http://mojave.caltech.edu/cs134/a/ October 27, 2014

  30. Hardware for address translation • Problem, each program references produces • 2 memory ops (paging, segmentation) • 3 memory ops (paged segmentation) • 4 memory ops (paged segmentation with paged tables) • Use an address-translation cache, called a translation lookaside buffer (TLB) Computing Systems Memory management http://mojave.caltech.edu/cs134/a/ October 27, 2014

  31. Translation Lookaside Buffer Computing Systems Memory management http://mojave.caltech.edu/cs134/a/ October 27, 2014

  32. Pentium General Memory Management Computing Systems Memory management http://mojave.caltech.edu/cs134/a/ October 27, 2014

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